Inventor · disambiguated record
Terrence Caskey
Also filed as: CASKEY TERRENCE · CASKEY TERRENCE C
38 granted patents·6 pending applications·475 citations·filing 2003–2018
97Inventor score
Files withINVENSAS CORP26VERTICAL CIRCUITS INC4MCELREA SIMON J S3CASKEY TERRENCE2UZOH CYPRIAN EMEKA2
Top patents by PatentIndex Score
44 records- 0199US8878353B2Structure for microelectronic packaging with bond elements to encapsulation surfaceINVENSAS CORP·Filed 2012·Granted Nov 4, 2014·137 cites·71 claims
- 0298US9502390B2BVA interposerINVENSAS CORP·Filed 2013·Granted Nov 22, 2016·59 cites·27 claims
- 0398US9095074B2Structure for microelectronic packaging with bond elements to encapsulation surfaceINVENSAS CORP·Filed 2014·Granted Jul 28, 2015·66 cites·20 claims
- 0497US9349669B2Reduced stress TSV and interposer structuresINVENSAS CORP·Filed 2015·Granted May 24, 2016·23 cites·25 claims
- 0597US9000600B2Reduced stress TSV and interposer structuresINVENSAS CORP·Filed 2014·Granted Apr 7, 2015·28 cites·15 claims
- 0694US7923349B2Wafer level surface passivation of stackable integrated circuit chipsVERTICAL CIRCUITS INC·Filed 2008·Granted Apr 12, 2011·37 cites·25 claims
- 0793US8884427B2Low CTE interposer without TSV structureINVENSAS CORP·Filed 2013·Granted Nov 11, 2014·13 cites·19 claims
- 0893US8723332B2Electrically interconnected stacked die assembliesMCELREA SIMON J S·Filed 2008·Granted May 13, 2014·35 cites·38 claims
- 0993US8629543B2Electrically interconnected stacked die assembliesMCELREA SIMON J S·Filed 2010·Granted Jan 14, 2014·19 cites·29 claims
- 1091US8981564B2Metal PVD-free conducting structuresINVENSAS CORP·Filed 2013·Granted Mar 17, 2015·11 cites·22 claims
- 1189US10297582B2BVA interposerINVENSAS CORP·Filed 2015·Granted May 21, 2019·6 cites·11 claims
- 1288US8723049B2Low-stress TSV design using conductive particlesWOYCHIK CHARLES G·Filed 2011·Granted May 13, 2014·9 cites·23 claims
- 1385US8772946B2Reduced stress TSV and interposer structuresUZOH CYPRIAN EMEKA·Filed 2012·Granted Jul 8, 2014·6 cites·83 claims
- 1482US9615456B2Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surfaceINVENSAS CORP·Filed 2015·Granted Apr 4, 2017·3 cites·20 claims
- 1579US9583475B2Microelectronic package with stacked microelectronic units and method for manufacture thereofINVENSAS CORP·Filed 2015·Granted Feb 28, 2017·2 cites·20 claims
- 1676US9433100B2Low-stress TSV design using conductive particlesTESSERA INC·Filed 2014·Granted Aug 30, 2016·3 cites·23 claims
- 1775US8723327B2Microelectronic package with stacked microelectronic units and method for manufacture thereofCASKEY TERRENCE·Filed 2011·Granted May 13, 2014·3 cites·18 claims
- 1874US9165911B2Microelectronic package with stacked microelectronic units and method for manufacture thereofINVENSAS CORP·Filed 2014·Granted Oct 20, 2015·2 cites·14 claims
- 1967US8324081B2Wafer level surface passivation of stackable integrated circuit chipsMCELREA SIMON J S·Filed 2011·Granted Dec 4, 2012·2 cites·9 claims
- 2066US9123780B2Method and structures for heat dissipating interposersINVENSAS CORP·Filed 2012·Granted Sep 1, 2015·1 cites·19 claims
- 2164US9601398B2Thin wafer handling and known good die test methodINVENSAS CORP·Filed 2014·Granted Mar 21, 2017·1 cites·15 claims
- 2263US9237648B2Carrier-less silicon interposerINVENSAS CORP·Filed 2013·Granted Jan 12, 2016·1 cites·19 claims
- 2363US8785790B2High strength through-substrate viasUZOH CYPRIAN EMEKA·Filed 2011·Granted Jul 22, 2014·1 cites·46 claims
- 2460US10475733B2Method and structures for heat dissipating interposersINVENSAS CORP·Filed 2018·Granted Nov 12, 2019·0 cites·9 claims
- 2557US9876002B2Microelectronic package with stacked microelectronic units and method for manufacture thereofINVENSAS CORP·Filed 2017·Granted Jan 23, 2018·0 cites·20 claims
- 2657US9558964B2Method of fabricating low CTE interposer without TSV structureINVENSAS CORP·Filed 2014·Granted Jan 31, 2017·0 cites·19 claims
- 2756US10103094B2Method and structures for heat dissipating interposersINVENSAS CORP·Filed 2017·Granted Oct 16, 2018·0 cites·20 claims
- 2855US10396114B2Method of fabricating low CTE interposer without TSV structureINVENSAS CORP·Filed 2017·Granted Aug 27, 2019·0 cites·17 claims
- 2955US7147735B2Vibratable die attachment toolINTEL CORP·Filed 2004·Granted Dec 12, 2006·7 cites·16 claims
- 3053US9685401B2Structures for heat dissipating interposersINVENSAS CORP·Filed 2015·Granted Jun 20, 2017·0 cites·16 claims
- 3152US9064933B2Methods and structure for carrier-less thin wafer handlingINVENSAS CORP·Filed 2012·Granted Jun 23, 2015·0 cites·15 claims
- 3251US9398700B2Method of forming a reliable microelectronic assemblyINVENSAS CORP·Filed 2013·Granted Jul 19, 2016·0 cites·15 claims
- 3350US9893030B2Reliable device assemblyINVENSAS CORP·Filed 2016·Granted Feb 13, 2018·0 cites·2 claims
- 3450US9379008B2Metal PVD-free conducting structuresINVENSAS CORP·Filed 2015·Granted Jun 28, 2016·0 cites·8 claims
- 3549US10181411B2Method for fabricating a carrier-less silicon interposerINVENSAS CORP·Filed 2015·Granted Jan 15, 2019·0 cites·10 claims
- 3649US9355905B2Methods and structure for carrier-less thin wafer handlingINVENSAS CORP·Filed 2015·Granted May 31, 2016·0 cites·14 claims
- 3749US8846447B2Thin wafer handling and known good die test methodWOYCHIK CHARLES G·Filed 2012·Granted Sep 30, 2014·0 cites·35 claims
- 3847US8742602B2Vertical electrical interconnect formed on support prior to die mountCASKEY TERRENCE·Filed 2008·Granted Jun 3, 2014·0 cites·20 claims
- 3945US2009068790A1Electrical Interconnect Formed by Pulsed DispenseVERTICAL CIRCUITS INC·Filed 2008·Application pending·0 cites
- 4045US2008315407A1Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabricationVERTICAL CIRCUITS INC·Filed 2008·Application pending·0 cites
- 4145US2009102038A1Chip scale stacked die packageVERTICAL CIRCUITS INC·Filed 2008·Application pending·0 cites
- 4240US2013070437A1Hybrid interposerMOHAMMED ILYAS·Filed 2011·Application pending·0 cites
- 4337US2006097403A1No-flow underfill materials for flip chipsLEBONHEUR VASSOUDEVANE·Filed 2004·Application pending·0 cites
- 4436US2005104180A1Electronic device with reduced entrapment of material between die and substrate electrical connectionsFiled 2003·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Terrence Caskey files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →