Inventor · disambiguated record
Tetsuo Hironaka
Also filed as: HIRONAKA TETSUO
8 granted patents·65 citations·filing 2003–2014
85Inventor score
Top patents by PatentIndex Score
8 records- 0181US7360024B2Multi-port integrated cacheSEMICONDUCTOR TECH ACAD RES CT·Filed 2003·Granted Apr 15, 2008·33 cites·5 claims
- 0274US9214209B2Semiconductor deviceTAIYO YUDEN KK·Filed 2014·Granted Dec 15, 2015·5 cites·13 claims
- 0374US8952721B2Semiconductor deviceISHIGURO TAKASHI·Filed 2011·Granted Feb 10, 2015·6 cites·14 claims
- 0470US7694077B2Multi-port integrated cacheSEMICONDUCTOR TECH ACAD RES CT·Filed 2008·Granted Apr 6, 2010·5 cites·11 claims
- 0561US8283945B2Semiconductor deviceHIRONAKA TETSUO·Filed 2010·Granted Oct 9, 2012·3 cites·20 claims
- 0652US7178008B2Register access scheduling method for multi-bank register file of a super-scalar parallel processorSEMICONDUCTOR TECH ACAD RES CT·Filed 2003·Granted Feb 13, 2007·7 cites·6 claims
- 0747US7117291B2Memory with synchronous bank architectureSEMICONDUCTOR TECH ACAD RES CT·Filed 2004·Granted Oct 3, 2006·6 cites·15 claims
- 0833US8964460B2Semiconductor device having a non-volatile memory built-inTAIYO YUDEN KK·Filed 2012·Granted Feb 24, 2015·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →