Inventor · disambiguated record
Terry L. Kendall
Also filed as: KENDALL TERRY · KENDALL TERRY L
19 granted patents·1,575 citations·filing 1988–2001
96Inventor score
Top patents by PatentIndex Score
19 records- 0198US6836816B2Flash memory low-latency cacheINTEL CORP·Filed 2001·Granted Dec 28, 2004·336 cites·19 claims
- 0298US6279069B1Interface for flash EEPROM memory arraysINTEL CORP·Filed 1996·Granted Aug 21, 2001·470 cites·32 claims
- 0392US6154819AApparatus and method using volatile lock and lock-down registers and for protecting memory blocksINTEL CORP·Filed 1998·Granted Nov 28, 2000·112 cites·11 claims
- 0490US6223290B1Method and apparatus for preventing the fraudulent use of a cellular telephoneINTEL CORP·Filed 1998·Granted Apr 24, 2001·166 cites·49 claims
- 0590US6009497AMethod and apparatus for updating flash memory resident firmware through a standard disk drive interfaceINTEL CORP·Filed 1998·Granted Dec 28, 1999·145 cites·15 claims
- 0681US5903496ASynchronous page-mode non-volatile memory with burst order circuitryINTEL CORP·Filed 1997·Granted May 11, 1999·44 cites·27 claims
- 0779US6222767B1Synchronous page-mode non-volatile memory with burst order circuitry and method thereofINTEL CORP·Filed 1999·Granted Apr 24, 2001·39 cites·21 claims
- 0878US6931498B2Status register architecture for flexible read-while-write deviceINTEL CORP·Filed 2001·Granted Aug 16, 2005·28 cites·12 claims
- 0977US6779045B2System and apparatus for increasing the number of operations per transmission for a media management systemINTEL CORP·Filed 2001·Granted Aug 17, 2004·27 cites·14 claims
- 1069US6216180B1Method and apparatus for a nonvolatile memory interface for burst read operationsINTEL CORP·Filed 1998·Granted Apr 10, 2001·28 cites·30 claims
- 1168US5696977APower management system for components used in battery powered applicationsINTEL CORP·Filed 1996·Granted Dec 9, 1997·37 cites·9 claims
- 1265US5603036APower management system for components used in battery powered applicationsINTEL CORP·Filed 1993·Granted Feb 11, 1997·37 cites·10 claims
- 1363US4939692ARead-only memory for microprocessor systems having shared address/data linesINTEL CORP·Filed 1988·Granted Jul 3, 1990·20 cites·4 claims
- 1462US6425062B1Controlling burst sequence in synchronous memoriesINTEL CORP·Filed 1999·Granted Jul 23, 2002·23 cites·6 claims
- 1551US6925558B2System and method for selecting and loading configuration data into a register through the use of a first and second reset signalINTEL CORP·Filed 2001·Granted Aug 2, 2005·7 cites·42 claims
- 1649US7007131B2Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memoryINTEL CORP·Filed 2000·Granted Feb 28, 2006·6 cites·18 claims
- 1749US5243700APort expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O portLARSEN ROBERT E·Filed 1992·Granted Sep 7, 1993·25 cites·14 claims
- 1845US5835933AMethod and apparatus for updating flash memory resident firmware through a standard disk drive interfaceINTEL CORP·Filed 1993·Granted Nov 10, 1998·14 cites·4 claims
- 1940US5430857AMethod and apparatus for translating logical addresses into physical addresses using odd/even translation tablesINTEL CORP·Filed 1993·Granted Jul 4, 1995·11 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →