Inventor · disambiguated record
Thomas Brennan
Also filed as: BRENNAN THOMAS · BRENNAN THOMAS C · BRENNAN THOMAS CHARLES
11 granted patents·226 citations·filing 1994–2012
90Inventor score
Top patents by PatentIndex Score
11 records- 0181US5629857AMethod and system for indicating a status of a circuit designIBM·Filed 1994·Granted May 13, 1997·93 cites·14 claims
- 0280US6711721B2Method for adding redundant vias on VLSI chipsIBM·Filed 2003·Granted Mar 23, 2004·25 cites·6 claims
- 0378US6715133B2Method for adding redundant vias on VLSI chipsIBM·Filed 2003·Granted Mar 30, 2004·22 cites·6 claims
- 0477US6556658B2Method for adding redundant vias on VLSI chipsIBM·Filed 2001·Granted Apr 29, 2003·21 cites·6 claims
- 0564US8766875B2Lightweight stiffener with integrated RF cavity-backed radiator for flexible RF emittersWILLIAMS ROBERT BRETT·Filed 2012·Granted Jul 1, 2014·3 cites·18 claims
- 0659US6434731B1Automated placement of signal distribution to diminish skew among same capacitance targets in integrated circuitsIBM·Filed 1999·Granted Aug 13, 2002·39 cites·10 claims
- 0745US9352820B2Device mount for an inflatable structureWILLIAMS ROBERT B·Filed 2012·Granted May 31, 2016·0 cites·10 claims
- 0845US7506276B2Method for isolating problem networks within an integrated circuit designIBM·Filed 2005·Granted Mar 17, 2009·0 cites·12 claims
- 0944US8352902B2Implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuitsIBM·Filed 2010·Granted Jan 8, 2013·0 cites·15 claims
- 1040US6260184B1Design of an integrated circuit by selectively reducing or maintaining power lines of the deviceIBM·Filed 1998·Granted Jul 10, 2001·13 cites·18 claims
- 1136US6041169AMethod and apparatus for performing integrated circuit timing including noiseIBM·Filed 1997·Granted Mar 21, 2000·10 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →