Inventor · disambiguated record
Thomas D. Fletcher
Also filed as: FLETCHER THOMAS · FLETCHER THOMAS D · FLETCHER THOMAS DALE
72 granted patents·4 pending applications·1,315 citations·filing 1981–2024
99Inventor score
Top patents by PatentIndex Score
76 records- 0197US11093277B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·25 claims
- 0297US10146535B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2016·Granted Dec 4, 2018·23 cites·22 claims
- 0396US11693691B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2021·Granted Jul 4, 2023·4 cites·11 claims
- 0496US11487541B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2020·Granted Nov 1, 2022·4 cites·34 claims
- 0593US5453708AClocking scheme for latching of a domino outputINTEL CORP·Filed 1995·Granted Sep 26, 1995·101 cites·13 claims
- 0692US6611920B1Clock distribution system for selectively enabling clock signals to portions of a pipelined circuitINTEL CORP·Filed 2000·Granted Aug 26, 2003·88 cites·38 claims
- 0791US11416281B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2016·Granted Aug 16, 2022·4 cites·28 claims
- 0890US12135981B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2023·Granted Nov 5, 2024·1 cites·20 claims
- 0989US9465580B2Math circuit for estimating a transcendental functionPINEIRO JOSE-ALEJANDRO·Filed 2011·Granted Oct 11, 2016·24 cites·19 claims
- 1089US6750689B2Method and apparatus for correcting a clock duty cycle in a clock distribution networkINTEL CORP·Filed 2001·Granted Jun 15, 2004·32 cites·17 claims
- 1187US10853065B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2018·Granted Dec 1, 2020·3 cites·22 claims
- 1287US10133577B2Vector mask driven clock gating for power efficiency of a processorINTEL CORP·Filed 2012·Granted Nov 20, 2018·8 cites·24 claims
- 1387US6323698B1Apparatus, method and system for providing LVS enables together with LVS dataINTEL CORP·Filed 2000·Granted Nov 27, 2001·33 cites·15 claims
- 1486US5942917AHigh speed ratioed CMOS logic structures for a pulsed input environmentINTEL CORP·Filed 1997·Granted Aug 24, 1999·52 cites·20 claims
- 1584US6448818B1Apparatus, method and system for a ratioed NOR logic arrangementINTEL CORP·Filed 2000·Granted Sep 10, 2002·28 cites·24 claims
- 1684US6346828B1Method and apparatus for pulsed clock tri-state controlINTEL CORP·Filed 2000·Granted Feb 12, 2002·40 cites·34 claims
- 1783US5241221ACMOS driver circuit having reduced switching noiseNORTH AMERICAN PHILIPS CORP SI·Filed 1992·Granted Aug 31, 1993·40 cites·15 claims
- 1883US2025060963A1Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2024·Application pending·0 cites
- 1982US2025123881A1Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2024·Application pending·0 cites
- 2081US6192092B1Method and apparatus for clock skew compensationINTEL CORP·Filed 1998·Granted Feb 20, 2001·135 cites·18 claims
- 2180US6487675B2Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 2001·Granted Nov 26, 2002·21 cites·53 claims
- 2279US5808225ACompressing music into a digital formatINTEL CORP·Filed 1996·Granted Sep 15, 1998·55 cites·20 claims
- 2378US6531897B1Global clock self-timed circuit with self-terminating precharge for high frequency applicationsINTEL CORP·Filed 2000·Granted Mar 11, 2003·21 cites·27 claims
- 2478US6055489ATemperature measurement and compensation schemeINTEL CORP·Filed 1997·Granted Apr 25, 2000·57 cites·26 claims
- 2577US12073214B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2022·Granted Aug 27, 2024·0 cites·23 claims
- 2677US9588765B2Instruction and logic for multiplier selectors for merging math functionsINTEL CORP·Filed 2014·Granted Mar 7, 2017·4 cites·20 claims
- 2777US6292401B1Method and apparatus for global bitline multiplexing for a high-speed memoryINTEL CORP·Filed 2000·Granted Sep 18, 2001·23 cites·15 claims
- 2876US9152382B2Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data valuesINTEL CORP·Filed 2012·Granted Oct 6, 2015·3 cites·23 claims
- 2976US4740717ASwitching device with dynamic hysteresisNORTH AMERICAN PHILIPS CORP SI·Filed 1986·Granted Apr 26, 1988·23 cites·20 claims
- 3076US4415817ABipolar logic gate including circuitry to prevent turn-off and deep saturation of pull-down transistorSIGNETICS CORP·Filed 1981·Granted Nov 15, 1983·19 cites·18 claims
- 3174US9323500B2Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data valuesHICKMANN BRIAN·Filed 2013·Granted Apr 26, 2016·5 cites·16 claims
- 3274US6442089B1Multi-level, low voltage swing sensing scheme for high speed memory designINTEL CORP·Filed 1999·Granted Aug 27, 2002·33 cites·27 claims
- 3373US9639355B2Functional unit capable of executing approximations of functionsINTEL CORP·Filed 2014·Granted May 2, 2017·3 cites·21 claims
- 3473US6256745B1Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 2000·Granted Jul 3, 2001·13 cites·21 claims
- 3572US6216234B1Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 1998·Granted Apr 10, 2001·49 cites·9 claims
- 3670US5250856ADifferential input buffer-inverters and gatesPHILIPS CORP·Filed 1991·Granted Oct 5, 1993·24 cites·39 claims
- 3769US9654143B2Consecutive bit error detection and correctionINTEL CORP·Filed 2014·Granted May 16, 2017·4 cites·15 claims
- 3868US4874971AEdge-sensitive dynamic switchNORTH AMERICAN PHILIPS CORP SI·Filed 1988·Granted Oct 17, 1989·14 cites·11 claims
- 3967US5828868AProcessor having execution core sections operating at different clock ratesINTEL CORP·Filed 1996·Granted Oct 27, 1998·38 cites·4 claims
- 4067US5155387ACircuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistorsPHILIPS CORP·Filed 1991·Granted Oct 13, 1992·21 cites·12 claims
- 4166US6828838B1Vectored flip-flops and latches with embedded output-merge logic and shared clock driversINTEL CORP·Filed 2003·Granted Dec 7, 2004·13 cites·37 claims
- 4265US9766886B2Instruction and logic to provide vector linear interpolation functionalityCORBAL JESUS·Filed 2011·Granted Sep 19, 2017·2 cites·27 claims
- 4364US9733935B2Super multiply add (super madd) instructionCORBAL JESUS·Filed 2011·Granted Aug 15, 2017·2 cites·21 claims
- 4461US6629255B1Generating a 2-phase clock using a non-50% divider circuitINTEL CORP·Filed 2000·Granted Sep 30, 2003·7 cites·15 claims
- 4560US9792115B2Super multiply add (super MADD) instructions with three scalar termsCORBAL JESUS·Filed 2011·Granted Oct 17, 2017·1 cites·21 claims
- 4660USRE44494EProcessor having execution core sections operating at different clock ratesSAGER DAVID J·Filed 2004·Granted Sep 10, 2013·5 cites·55 claims
- 4760US6204714B1Variable width pulse generatorINTEL CORP·Filed 1998·Granted Mar 20, 2001·14 cites·21 claims
- 4858US6667645B1Pulsed clock signal transfer circuits with dynamic latchingINTEL CORP·Filed 1999·Granted Dec 23, 2003·34 cites·31 claims
- 4957US7325025B2Look-ahead carry adder circuitINTEL CORP·Filed 2001·Granted Jan 29, 2008·5 cites·25 claims
- 5057US6242958B1Master slave flip flop as a dynamic latchINTEL CORP·Filed 1999·Granted Jun 5, 2001·16 cites·29 claims
Showing the top 50 of 76 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →