Inventor · disambiguated record
Thomas B. Huang
Also filed as: HUANG THOMAS B · HUANG THOMAS CHI-TUNG
11 granted patents·5 pending applications·925 citations·filing 1991–2010
94Inventor score
Files withQUICKTURN DESIGN SYSTEMS INC7CHANG CHIOUMIN M3HUANG THOMAS B2I CUBE DESIGN SYSTEMS INC1INPA SYSTEMS INC1
Top patents by PatentIndex Score
16 records- 0194US5425036AMethod and apparatus for debugging reconfigurable emulation systemsQUICKTURN DESIGN SYSTEMS INC·Filed 1992·Granted Jun 13, 1995·389 cites·11 claims
- 0291US5475830AStructure and method for providing a reconfigurable emulation circuit without hold time violationsQUICKTURN DESIGN SYSTEMS INC·Filed 1992·Granted Dec 12, 1995·175 cites·21 claims
- 0390US7353162B2Scalable reconfigurable prototyping system and methodS2C INC·Filed 2005·Granted Apr 1, 2008·36 cites·63 claims
- 0484US5202593ABi-directional bus repeaterI CUBE DESIGN SYSTEMS INC·Filed 1991·Granted Apr 13, 1993·45 cites·7 claims
- 0582US5835751AStructure and method for providing reconfigurable emulation circuitQUICKTURN DESIGN SYSTEMS INC·Filed 1997·Granted Nov 10, 1998·78 cites·4 claims
- 0678US8136065B2Integrated prototyping system for validating an electronic system designHUANG THOMAS B·Filed 2008·Granted Mar 13, 2012·14 cites·29 claims
- 0776US5448522AMulti-port memory emulation using tag registersQUICKTURN DESIGN SYSTEMS INC·Filed 1994·Granted Sep 5, 1995·34 cites·5 claims
- 0875US5940603AMethod and apparatus for emulating multi-ported memory circuitsQUICKTURN DESIGN SYSTEMS INC·Filed 1997·Granted Aug 17, 1999·77 cites·26 claims
- 0971US7908576B2Method of progressively prototyping and validating a customer's electronic system designINPA SYSTEMS INC·Filed 2007·Granted Mar 15, 2011·9 cites·19 claims
- 1064US5649167AMethods for controlling timing in a logic emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Jul 15, 1997·38 cites·1 claims
- 1158US5563829AMulti-port memory emulation using tag registersQUICKTURN DESIGN SYSTEMS INC·Filed 1995·Granted Oct 8, 1996·30 cites·4 claims
- 1246US2010305933A1Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector SubstitutionCHANG CHIOUMIN M·Filed 2009·Application pending·0 cites
- 1345US2010100860A1Method and apparatus for debugging an electronic system design (esd) prototypeCHANG CHIOUMIN M·Filed 2008·Application pending·0 cites
- 1441US2004203172A1Method and apparatus for a chemical sensorURS CORP·Filed 2003·Application pending·0 cites
- 1537US2012005547A1Scalable system debugger for prototype debuggingCHANG CHIOUMIN M·Filed 2010·Application pending·0 cites
- 1633US2011289469A1Virtual interconnection method and apparatusHUANG THOMAS B·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →