Inventor · disambiguated record
Thomas F. Hummel
Also filed as: HUMMEL THOMAS · HUMMEL THOMAS F · HUMMEL THOMAS FREDERICK
20 granted patents·1 pending application·256 citations·filing 2001–2023
94Inventor score
Files withCAVIUM INC6MARVELL ASIA PTE LTD5CAVIUM NETWORKS INC2HEWLETT PACKARD DEVELOPMENT CO2ASTRIUM GMBH1
Top patents by PatentIndex Score
21 records- 0196US7535907B2TCP engineCAVIUM NETWORKS INC·Filed 2005·Granted May 19, 2009·77 cites·16 claims
- 0291US9219560B2Multi-protocol SerDes PHY apparatusHUMMEL THOMAS F·Filed 2011·Granted Dec 22, 2015·17 cites·18 claims
- 0388US11036643B1Mid-level instruction cacheMARVELL ASIA PTE LTD·Filed 2019·Granted Jun 15, 2021·5 cites·12 claims
- 0488US7895431B2Packet queuing, scheduling and orderingCAVIUM NETWORKS INC·Filed 2004·Granted Feb 22, 2011·78 cites·31 claims
- 0583US9379992B2Method and an apparatus for virtualization of a quality-of-serviceCAVIUM INC·Filed 2013·Granted Jun 28, 2016·7 cites·24 claims
- 0683US6691207B2Method and apparatus for implementing loop compression in a program counter traceHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 10, 2004·37 cites·33 claims
- 0781US11119929B2Low latency inter-chip communication mechanism in multi-chip processing systemCAVIUM LLC·Filed 2019·Granted Sep 14, 2021·2 cites·20 claims
- 0881US9870328B2Managing buffered communication between coresCAVIUM INC·Filed 2014·Granted Jan 16, 2018·6 cites·12 claims
- 0980US9501425B2Translation lookaside buffer managementCAVIUM INC·Filed 2014·Granted Nov 22, 2016·6 cites·26 claims
- 1078US8634509B2Synchronized clock phase interpolatorCRAIN ETHAN·Filed 2012·Granted Jan 21, 2014·7 cites·10 claims
- 1175US12019552B2Low latency inter-chip communication mechanism in a multi-chip processing systemMARVELL ASIA PTE LTD·Filed 2023·Granted Jun 25, 2024·0 cites·20 claims
- 1272US9665505B2Managing buffered communication between socketsCAVIUM INC·Filed 2014·Granted May 30, 2017·3 cites·16 claims
- 1369US11620223B2Low latency inter-chip communication mechanism in a multi-chip processing systemMARVELL ASIA PTE LTD·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 1467US9264385B2Messaging with flexible transmit orderingCAVIUM INC·Filed 2015·Granted Feb 16, 2016·1 cites·22 claims
- 1565US9065781B2Messaging with flexible transmit orderingCAVIUM INC·Filed 2013·Granted Jun 23, 2015·1 cites·22 claims
- 1656US7031869B2Method and apparatus for managing timestamps when storing dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Apr 18, 2006·9 cites·33 claims
- 1752US11379379B1Differential cache block sizing for computing systemsMARVELL ASIA PTE LTD·Filed 2020·Granted Jul 5, 2022·0 cites·23 claims
- 1849US11379368B1External way allocation circuitry for processor coresMARVELL ASIA PTE LTD·Filed 2020·Granted Jul 5, 2022·0 cites·22 claims
- 1949US9596193B2Messaging with flexible transmit orderingKESSLER RICHARD E·Filed 2011·Granted Mar 14, 2017·0 cites·18 claims
- 2047US11327759B2Managing low-level instructions and core interactions in multi-core processorsMARVELL INT LTD·Filed 2018·Granted May 10, 2022·0 cites·24 claims
- 2146US2014260553A1Detection device for detecting at least one fault stateASTRIUM GMBH·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →