Inventor · disambiguated record
Thomas F. Joyce
Also filed as: HOLTEY THOMAS O · JOYCE THOMAS F
43 granted patents·1,543 citations·filing 1976–1997
99Inventor score
Files withHONEYWELL INF SYSTEMS21BULL HN INFORMATION SYST11HONEYWELL BULL4NEC CORP2PACKARD BELL NEC2
Top patents by PatentIndex Score
43 records- 0192US4695943AMultiprocessor shared pipeline cache memory with split cycle and concurrent utilizationHONEYWELL INF SYSTEMS·Filed 1984·Granted Sep 22, 1987·113 cites·33 claims
- 0289US5517648ASymmetric multiprocessing system with unified environment and distributed system functionsZENITH DATA SYSTEMS CORP·Filed 1995·Granted May 14, 1996·119 cites·3 claims
- 0388US4161024APrivate cache-to-CPU interface in a bus oriented data processing systemHONEYWELL INF SYSTEMS·Filed 1977·Granted Jul 10, 1979·59 cites·3 claims
- 0487US4157587AHigh speed buffer memory system with word prefetchHONEYWELL INF SYSTEMS·Filed 1977·Granted Jun 5, 1979·35 cites·20 claims
- 0586US4785398AVirtual cache system using page level number generating CAM to access other memories for processing requests relating to a pageHONEYWELL BULL·Filed 1985·Granted Nov 15, 1988·98 cites·22 claims
- 0685US4190885AOut of store indicator for a cache store in test modeHONEYWELL INF SYSTEMS·Filed 1977·Granted Feb 26, 1980·34 cites·9 claims
- 0783US5193181ARecovery method and apparatus for a pipelined processing unit of a multiprocessor systemBULL HN INFORMATION SYST·Filed 1990·Granted Mar 9, 1993·102 cites·18 claims
- 0882US4813002AHigh speed high density dynamic address translatorHONEYWELL BULL·Filed 1986·Granted Mar 14, 1989·77 cites·32 claims
- 0981US5809340AAdaptively generating timing signals for access to various memory devices based on stored profilesPACKARD BELL NEC·Filed 1997·Granted Sep 15, 1998·99 cites·5 claims
- 1081US5148533AApparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache unitsBULL HN INFORMATION SYST·Filed 1989·Granted Sep 15, 1992·73 cites·20 claims
- 1181US4195340AFirst in first out activity queue for a cache storeHONEYWELL INF SYSTEMS·Filed 1977·Granted Mar 25, 1980·43 cites·10 claims
- 1281US4118773AMicroprogram memory bank addressing systemHONEYWELL INF SYSTEMS·Filed 1977·Granted Oct 3, 1978·45 cites·7 claims
- 1380US4195342AMulti-configurable cache store systemHONEYWELL INF SYSTEMS·Filed 1977·Granted Mar 25, 1980·42 cites·2 claims
- 1480US4167782AContinuous updating of cache storeHONEYWELL INF SYSTEMS·Filed 1977·Granted Sep 11, 1979·43 cites·13 claims
- 1575US4323967ALocal bus interface for controlling information transfers between units in a central subsystemHONEYWELL INF SYSTEMS·Filed 1980·Granted Apr 6, 1982·45 cites·8 claims
- 1675US4195341AInitialization of cache store to assure valid dataHONEYWELL INF SYSTEMS·Filed 1977·Granted Mar 25, 1980·22 cites·18 claims
- 1772US5430862AEmulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC executionBULL HN INFORMATION SYST·Filed 1990·Granted Jul 4, 1995·68 cites·20 claims
- 1871US5053951ASegment descriptor unit for performing static and dynamic address translation operationsBULL HN INFORMATION SYST·Filed 1989·Granted Oct 1, 1991·45 cites·22 claims
- 1967US4195343ARound robin replacement for a cache storeHONEYWELL INF SYSTEMS·Filed 1977·Granted Mar 25, 1980·26 cites·10 claims
- 2063US4124893AMicroword address branching bit arrangementHONEYWELL INF SYSTEMS·Filed 1976·Granted Nov 7, 1978·24 cites·5 claims
- 2162US5283870AMethod and apparatus for avoiding processor deadly embrace in a multiprocessor systemBULL HN INFORMATION SYST·Filed 1991·Granted Feb 1, 1994·40 cites·10 claims
- 2262US4295203AAutomatic rounding of floating point operandsHONEYWELL INF SYSTEMS·Filed 1979·Granted Oct 13, 1981·22 cites·7 claims
- 2360US4641305AControl store memory read error resiliency method and apparatusHONEYWELL INF SYSTEMS·Filed 1984·Granted Feb 3, 1987·23 cites·14 claims
- 2458US4214303AWord oriented high speed buffer memory system connected to a system busHONEYWELL INF SYSTEMS·Filed 1977·Granted Jul 22, 1980·20 cites·11 claims
- 2557US6311286B1Symmetric multiprocessing system with unified environment and distributed system functionsNEC CORP·Filed 1994·Granted Oct 30, 2001·20 cites·4 claims
- 2656US4783735ALeast recently used replacement level generating apparatusHONEYWELL BULL·Filed 1985·Granted Nov 8, 1988·24 cites·9 claims
- 2752US5341495ABus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocolsBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·25 cites·15 claims
- 2850US5956522ASymmetric multiprocessing system with unified environment and distributed system functionsPACKARD BELL NEC·Filed 1995·Granted Sep 21, 1999·15 cites·1 claims
- 2950US5123097AApparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategyBULL HN INFORMATION SYST·Filed 1989·Granted Jun 16, 1992·18 cites·17 claims
- 3050US4087857AROM-initializing apparatusHONEYWELL INF SYSTEMS·Filed 1976·Granted May 2, 1978·14 cites·7 claims
- 3149US4105978AStretch and stall clockHONEYWELL INF SYSTEMS·Filed 1976·Granted Aug 8, 1978·12 cites·9 claims
- 3244US5287522AExternal procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chipBULL HN INFORMATION SYST·Filed 1990·Granted Feb 15, 1994·16 cites·14 claims
- 3343US4942547AMultiprocessors on a single semiconductor chipHONEYWELL BULL·Filed 1987·Granted Jul 17, 1990·12 cites·8 claims
- 3442US5051894AApparatus and method for address translation of non-aligned double word virtual addressesBULL HN INFORMATION SYST·Filed 1989·Granted Sep 24, 1991·12 cites·16 claims
- 3542US4670835ADistributed control store word architectureHONEYWELL INF SYSTEMS·Filed 1984·Granted Jun 2, 1987·11 cites·8 claims
- 3642US4308589AApparatus for performing the scientific add instructionHONEYWELL INF SYSTEMS·Filed 1979·Granted Dec 29, 1981·9 cites·14 claims
- 3739US5522069ASymmetric multiprocessing system with unified environment and distributed system functionsZENITH DATA SYSTEMS CORP·Filed 1994·Granted May 28, 1996·7 cites·1 claims
- 3836US5148530AMethod for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bitsBULL HN INFORMATION SYST·Filed 1989·Granted Sep 15, 1992·6 cites·3 claims
- 3935US5341508AProcessing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous busBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·7 cites·14 claims
- 4035US4305134AAutomatic operand length control of the result of a scientific arithmetic operationHONEYWELL INF SYSTEMS·Filed 1979·Granted Dec 8, 1981·5 cites·6 claims
- 4134US4901222AMethod and apparatus for backing out of a software instruction after execution has begunBULL NH INFORMATION SYSTEMS IN·Filed 1987·Granted Feb 13, 1990·6 cites·11 claims
- 4232US6125436ASymmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address spaceNEC CORP·Filed 1997·Granted Sep 26, 2000·3 cites·8 claims
- 4332US4107774AMicroprogram splatter return apparatusHONEYWELL INF SYSTEMS·Filed 1976·Granted Aug 15, 1978·4 cites·8 claims
Join the waitlist — get patent alerts
Get an alert when Thomas F. Joyce files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →