Inventor · disambiguated record
Thomas J. Knips
Also filed as: KNIPS THOMAS J
21 granted patents·1 pending application·141 citations·filing 2001–2024
94Inventor score
Files withIBM22
Top patents by PatentIndex Score
22 records- 0191US7064990B1Method and apparatus for implementing multiple column redundancy for memoryIBM·Filed 2005·Granted Jun 20, 2006·29 cites·17 claims
- 0289US7437626B2Efficient method of test and soft repair of SRAM with redundancyIBM·Filed 2005·Granted Oct 14, 2008·21 cites·3 claims
- 0388US9136019B1Built-in testing of unused element on chipIBM·Filed 2014·Granted Sep 15, 2015·10 cites·9 claims
- 0480US7793173B2Efficient memory product for test and soft repair of SRAM with redundancyIBM·Filed 2008·Granted Sep 7, 2010·11 cites·3 claims
- 0578US7930601B2AC ABIST diagnostic method, apparatus and program productIBM·Filed 2008·Granted Apr 19, 2011·11 cites·16 claims
- 0669US7219275B2Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancyIBM·Filed 2005·Granted May 15, 2007·7 cites·16 claims
- 0763US9355746B2Built-in testing of unused element on chipIBM·Filed 2014·Granted May 31, 2016·2 cites·14 claims
- 0862US7076706B2Method and apparatus for ABIST diagnosticsIBM·Filed 2001·Granted Jul 11, 2006·10 cites·7 claims
- 0961US11081202B2Failing address registers for built-in self testsIBM·Filed 2019·Granted Aug 3, 2021·1 cites·17 claims
- 1058US7076710B2Non-binary address generation for ABISTIBM·Filed 2003·Granted Jul 11, 2006·10 cites·9 claims
- 1158US7068554B1Apparatus and method for implementing multiple memory redundancy with delay tracking clockIBM·Filed 2005·Granted Jun 27, 2006·4 cites·17 claims
- 1255US7529997B2Method for self-correcting cache using line delete, data logging, and fuse repair correctionIBM·Filed 2005·Granted May 5, 2009·3 cites·1 claims
- 1350US7170320B2Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steeringIBM·Filed 2005·Granted Jan 30, 2007·1 cites·19 claims
- 1450US6584023B1System for implementing a column redundancy scheme for arrays with controls that span multiple data bitsIBM·Filed 2002·Granted Jun 24, 2003·6 cites·9 claims
- 1549US7009895B2Method for skip over redundancy decode with very low overheadIBM·Filed 2004·Granted Mar 7, 2006·5 cites·10 claims
- 1649US2025279148A1Reconfigurable testing of an integrated circuitIBM·Filed 2024·Application pending·0 cites
- 1747US7380191B2ABIST data compression and serialization for memory built-in self test of SRAM with redundancyIBM·Filed 2005·Granted May 27, 2008·1 cites·6 claims
- 1847US7073105B2ABIST address generationIBM·Filed 2003·Granted Jul 4, 2006·5 cites·11 claims
- 1945US11657887B2Testing bit write operation to a memory array in integrated circuitsIBM·Filed 2021·Granted May 23, 2023·0 cites·17 claims
- 2045US11069422B1Testing multi-port array in integrated circuitsIBM·Filed 2020·Granted Jul 20, 2021·0 cites·20 claims
- 2145US7210084B2Integrated system logic and ABIST data compression for an SRAM directoryIBM·Filed 2003·Granted Apr 24, 2007·4 cites·5 claims
- 2240US9983261B2Partition-able storage of test results using inactive storage elementsIBM·Filed 2016·Granted May 29, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →