Inventor · disambiguated record
Thomas Koehler
Also filed as: KOEHLER THOMAS · Koehler thomas g
23 granted patents·1 pending application·59 citations·filing 1993–2022
93Inventor score
Top patents by PatentIndex Score
24 records- 0192US10380033B2Multi-engine address translation facilityIBM·Filed 2017·Granted Aug 13, 2019·6 cites·8 claims
- 0289US10083124B1Translating virtual memory addresses to physical addressesIBM·Filed 2017·Granted Sep 25, 2018·6 cites·20 claims
- 0379US10025608B2Quiesce handling in multithreaded environmentsIBM·Filed 2014·Granted Jul 17, 2018·4 cites·8 claims
- 0475US10380032B2Multi-engine address translation facilityIBM·Filed 2017·Granted Aug 13, 2019·1 cites·14 claims
- 0572US10127159B1Link consistency in a hierarchical TLB with concurrent table walksIBM·Filed 2017·Granted Nov 13, 2018·1 cites·8 claims
- 0670US8135960B2Multiprocessor electronic circuit including a plurality of processors and electronic data processing systemKOEHLER THOMAS·Filed 2008·Granted Mar 13, 2012·4 cites·8 claims
- 0768US10956341B2Multi-engine address translation facilityIBM·Filed 2020·Granted Mar 23, 2021·0 cites·18 claims
- 0866US10635603B2Multi-engine address translation facilityIBM·Filed 2019·Granted Apr 28, 2020·0 cites·7 claims
- 0966US10621105B2Multi-engine address translation facilityIBM·Filed 2019·Granted Apr 14, 2020·0 cites·14 claims
- 1066US9658852B2Updating of shadow registers in N:1 clock domainIBM·Filed 2015·Granted May 23, 2017·1 cites·20 claims
- 1165US9715458B2Multiprocessor computer systemIBM·Filed 2015·Granted Jul 25, 2017·1 cites·20 claims
- 1264US10929312B2Zone-SDID mapping scheme for TLB purgesIBM·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 1364US8166249B2Performing a least recently used (LRU) algorithm for a co-processorKOEHLER THOMAS·Filed 2009·Granted Apr 24, 2012·3 cites·20 claims
- 1463US8594321B2Apparatus and method for operating a symmetric cipher engine in cipher-block chaining modeMAYER ULRICH·Filed 2008·Granted Nov 26, 2013·2 cites·8 claims
- 1560US10353828B2Zone-SDID mapping scheme for TLB purgesIBM·Filed 2017·Granted Jul 16, 2019·0 cites·7 claims
- 1659US10353827B2Zone-SDID mapping scheme for TLB purgesIBM·Filed 2017·Granted Jul 16, 2019·0 cites·13 claims
- 1758US10140217B1Link consistency in a hierarchical TLB with concurrent table walksIBM·Filed 2017·Granted Nov 27, 2018·0 cites·12 claims
- 1857US10176002B2Quiesce handling in multithreaded environmentsIBM·Filed 2014·Granted Jan 8, 2019·0 cites·4 claims
- 1955US11775444B1Fetch request arbiterIBM·Filed 2022·Granted Oct 3, 2023·0 cites·17 claims
- 2054US5996063AManagement of both renamed and architected registers in a superscalar computer systemIBM·Filed 1997·Granted Nov 30, 1999·28 cites·13 claims
- 2145US8250336B2Method, system and computer program product for storing external device result dataSHUM CHUNG-LUNG KEVIN·Filed 2008·Granted Aug 21, 2012·0 cites·17 claims
- 2241US2001004747A1Method and system for operating a computer systemIBM·Filed 2000·Application pending·0 cites
- 2340US8966221B2Translating translation requests having associated prioritiesGAERTNER UTE·Filed 2011·Granted Feb 24, 2015·0 cites·20 claims
- 2429US5694400AChecking data integrity in buffered data transmissionIBM·Filed 1993·Granted Dec 2, 1997·2 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →