Inventor · disambiguated record
Thomas J. Massingill
Also filed as: MASSINGILL THOMAS · MASSINGILL THOMAS J · MASSINGILL THOMAS JOEL
17 granted patents·2,034 citations·filing 1991–2005
96Inventor score
Files withFUJITSU LTD8VLSI TECHNOLOGY INC3DIGITAL EQUIPMENT CORP2MASSINGILL THOMAS JOEL2VLSI TECHNOLOGY1
Top patents by PatentIndex Score
17 records- 0198US6690845B1Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for makingFUJITSU LTD·Filed 2000·Granted Feb 10, 2004·334 cites·19 claims
- 0298US6343171B1Systems based on opto-electronic substrates with electrical and optical interconnections and methods for makingFUJITSU LTD·Filed 1999·Granted Jan 29, 2002·429 cites·26 claims
- 0397US6845184B1Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for makingFUJITSU LTD·Filed 1999·Granted Jan 18, 2005·286 cites·25 claims
- 0496US6882045B2Multi-chip module and method for forming and method for deplating defective capacitorsFiled 2001·Granted Apr 19, 2005·99 cites·9 claims
- 0596US6611635B1Opto-electronic substrates with electrical and optical interconnections and methods for makingFUJITSU LTD·Filed 1999·Granted Aug 26, 2003·193 cites·45 claims
- 0694US5420460AThin cavity down ball grid array package based on wirebond technologyVLSI TECHNOLOGY INC·Filed 1993·Granted May 30, 1995·195 cites·24 claims
- 0793US6326555B1Method and structure of z-connected laminated substrate for high density electronic packagingFUJITSU LTD·Filed 1999·Granted Dec 4, 2001·93 cites·44 claims
- 0892US6163957AMultilayer laminated substrates with high density interconnects and methods of making the sameFUJITSU LTD·Filed 1998·Granted Dec 26, 2000·138 cites·19 claims
- 0988US6271107B1Semiconductor with polymeric layerFUJITSU LTD·Filed 1999·Granted Aug 7, 2001·95 cites·33 claims
- 1078US5561328APhoto-definable template for semiconductor chip alignmentDIGITAL EQUIPMENT CORP·Filed 1995·Granted Oct 1, 1996·48 cites·8 claims
- 1172US5947751AProduction and test socket for ball grid array semiconductor packageVLSI TECHNOLOGY INC·Filed 1998·Granted Sep 7, 1999·34 cites·2 claims
- 1268US5587336ABump formation on yielded semiconductor diesVLSI TECHNOLOGY·Filed 1994·Granted Dec 24, 1996·46 cites·3 claims
- 1367US6448106B1Modules with pins and methods for making modules with pinsFUJITSU LTD·Filed 1999·Granted Sep 10, 2002·26 cites·16 claims
- 1455US7489517B2Die down semiconductor packageMASSINGILL THOMAS JOEL·Filed 2005·Granted Feb 10, 2009·1 cites·8 claims
- 1554US7239024B2Semiconductor package with recess for dieMASSINGILL THOMAS JOEL·Filed 2003·Granted Jul 3, 2007·7 cites·7 claims
- 1642US5413964APhoto-definable template for semiconductor chip alignmentDIGITAL EQUIPMENT CORP·Filed 1991·Granted May 9, 1995·10 cites·13 claims
- 1730US6380001B1Flexible pin count package for semiconductor deviceVLSI TECHNOLOGY INC·Filed 1999·Granted Apr 30, 2002·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →