Inventor · disambiguated record
Thang Q. Nguyen
Also filed as: NGUYEN THANG Q · NGUYEN THANG QUANG
15 granted patents·1 pending application·161 citations·filing 1997–2024
90Inventor score
Top patents by PatentIndex Score
16 records- 0176US7240041B2Network message processing using inverse pattern matchingFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jul 3, 2007·23 cites·30 claims
- 0275US5812881AHandshake minimizing serial to parallel bus interface in a data processing systemIBM·Filed 1997·Granted Sep 22, 1998·71 cites·3 claims
- 0368US9448741B2Piggy-back snoops for non-coherent memory transactions within distributed processing systemsDESHPANDE SANJAY R·Filed 2014·Granted Sep 20, 2016·2 cites·20 claims
- 0463US6122683AHandshake minimizing serial-to-parallel interface with shift register coupled by parallel bus to address logic and control logicIBM·Filed 1998·Granted Sep 19, 2000·40 cites·6 claims
- 0562US9720847B2Least recently used (LRU) cache replacement implementation using a FIFO storing indications of whether a way of the cache was most recently accessedFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Aug 1, 2017·1 cites·18 claims
- 0662US9501442B2Configurable peripheral componenent interconnect express (PCIe) controllerKRAMER DAVID B·Filed 2014·Granted Nov 22, 2016·2 cites·20 claims
- 0761US7613775B2Network message filtering using hashing and pattern matchingFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Nov 3, 2009·7 cites·52 claims
- 0858US7480837B2Method of monitoring timeout conditions and device thereforFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jan 20, 2009·2 cites·19 claims
- 0955US2024348562A1Multi-host isolation in a shared networking pipelineINTEL CORP·Filed 2024·Application pending·0 cites
- 1050US9665518B2Methods and systems for controlling ordered write transactions to multiple devices using switch point networksDESHPANDE SANJAY R·Filed 2014·Granted May 30, 2017·0 cites·24 claims
- 1143US8090892B2Ordered queue and methods thereforNGUYEN THANG Q·Filed 2009·Granted Jan 3, 2012·0 cites·20 claims
- 1241US9195625B2Interconnect controller for a data processing device with transaction tag locking and method thereforIKONOMOPOULOS GUS P·Filed 2009·Granted Nov 24, 2015·0 cites·20 claims
- 1340US9632933B2Efficient coherency response mechanismFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Apr 25, 2017·0 cites·17 claims
- 1440US5931931AMethod for bus arbitration in a multiprocessor systemIBM·Filed 1997·Granted Aug 3, 1999·13 cites·10 claims
- 1539US9497141B2Switch point having look-ahead bypassFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Nov 15, 2016·0 cites·16 claims
- 1635US8775699B2Read stacking for data processor interfaceNGUYEN THANG Q·Filed 2011·Granted Jul 8, 2014·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →