Inventor · disambiguated record
Thomas Andrew Sartorius
Also filed as: SARTORIUS THOMAS · SARTORIUS THOMAS A · SARTORIUS THOMAS ANDREW
107 granted patents·16 pending applications·1,375 citations·filing 1991–2021
99Inventor score
Files withQUALCOMM INC57IBM37MICROSOFT TECHNOLOGY LICENSING LLC4SARTORIUS THOMAS ANDREW4SMITH RODNEY W3
Top patents by PatentIndex Score
123 records- 0190US9086813B2Method and apparatus to save and restore system memory management unit (MMU) contextsQUALCOMM INC·Filed 2013·Granted Jul 21, 2015·13 cites·21 claims
- 0290US7624256B2System and method wherein conditional instructions unconditionally provide outputQUALCOMM INC·Filed 2005·Granted Nov 24, 2009·24 cites·15 claims
- 0389US7152155B2System and method of correcting a branch mispredictionQUALCOMM INC·Filed 2005·Granted Dec 19, 2006·19 cites·17 claims
- 0488US5996092ASystem and method for tracing program execution within a processor before and after a triggering eventIBM·Filed 1996·Granted Nov 30, 1999·127 cites·4 claims
- 0587US7624254B2Segmented pipeline flushing for mispredicted branchesQUALCOMM INC·Filed 2007·Granted Nov 24, 2009·18 cites·1 claims
- 0687US7278012B2Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructionsQUALCOMM INC·Filed 2005·Granted Oct 2, 2007·18 cites·22 claims
- 0786US7587580B2Power efficient instruction prefetch mechanismQUALCOMM INC·Filed 2005·Granted Sep 8, 2009·14 cites·11 claims
- 0885US7676659B2System, method and software to preload instructions from a variable-length instruction set with proper pre-decodingQUALCOMM INC·Filed 2007·Granted Mar 9, 2010·14 cites·24 claims
- 0985US7500045B2Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing systemQUALCOMM INC·Filed 2005·Granted Mar 3, 2009·15 cites·21 claims
- 1085US7366869B2Method and system for optimizing translation lookaside buffer entriesQUALCOMM INC·Filed 2005·Granted Apr 29, 2008·15 cites·14 claims
- 1183US6826747B1System and method for tracing program instructions before and after a trace triggering event within a processorIBM·Filed 1999·Granted Nov 30, 2004·88 cites·19 claims
- 1283US6826656B2Reducing power in a snooping cache based multiprocessor environmentIBM·Filed 2002·Granted Nov 30, 2004·35 cites·27 claims
- 1382US7711927B2System, method and software to preload instructions from an instruction set other than one currently executingQUALCOMM INC·Filed 2007·Granted May 4, 2010·10 cites·19 claims
- 1482US5367653AReconfigurable multi-way associative cache memoryIBM·Filed 1991·Granted Nov 22, 1994·108 cites·10 claims
- 1580US6081860AAddress pipelining for data transfersIBM·Filed 1997·Granted Jun 27, 2000·92 cites·15 claims
- 1679US8386716B2Apparatus and methods to reduce castouts in a multi-level cache hierarchyQUALCOMM INC·Filed 2011·Granted Feb 26, 2013·4 cites·29 claims
- 1779US7805588B2Caching memory attribute indicators with cached memory data fieldQUALCOMM INC·Filed 2005·Granted Sep 28, 2010·9 cites·26 claims
- 1879US7426626B2TLB lock indicatorQUALCOMM INC·Filed 2005·Granted Sep 16, 2008·9 cites·18 claims
- 1979US7421568B2Power saving methods and apparatus to selectively enable cache bits based on known processor stateQUALCOMM INC·Filed 2005·Granted Sep 2, 2008·9 cites·18 claims
- 2079US5910930ADynamic control of power management circuitryIBM·Filed 1997·Granted Jun 8, 1999·92 cites·7 claims
- 2178US8078803B2Apparatus and methods to reduce castouts in a multi-level cache hierarchySPEIER THOMAS PHILIP·Filed 2008·Granted Dec 13, 2011·8 cites·29 claims
- 2277US9606818B2Systems and methods of executing multiple hypervisors using multiple sets of processorsQUALCOMM INC·Filed 2013·Granted Mar 28, 2017·4 cites·31 claims
- 2377US8938602B2Multiple sets of attribute fields within a single page table entrySHARP COLIN CHRISTOPHER·Filed 2012·Granted Jan 20, 2015·5 cites·28 claims
- 2476US9026744B2Enforcing strongly-ordered requests in a weakly-ordered processingHOFMANN RICHARD GERARD·Filed 2005·Granted May 5, 2015·8 cites·17 claims
- 2575US9063749B2Hardware support for hashtables in dynamic languagesCEZE LUIS·Filed 2011·Granted Jun 23, 2015·4 cites·58 claims
- 2675US7437537B2Methods and apparatus for predicting unaligned memory accessQUALCOMM INC·Filed 2005·Granted Oct 14, 2008·7 cites·18 claims
- 2774US7478228B2Apparatus for generating return address predictions for implicit and explicit subroutine callsQUALCOMM INC·Filed 2006·Granted Jan 13, 2009·5 cites·13 claims
- 2874US7415638B2Pre-decode error handling via branch correctionQUALCOMM INC·Filed 2004·Granted Aug 19, 2008·17 cites·22 claims
- 2974US7281118B2Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessorIBM·Filed 2005·Granted Oct 9, 2007·6 cites·17 claims
- 3074US5925118AMethods and architectures for overlapped read and write operationsIBM·Filed 1996·Granted Jul 20, 1999·69 cites·39 claims
- 3173US10114756B2Externally programmable memory management unitQUALCOMM INC·Filed 2013·Granted Oct 30, 2018·3 cites·35 claims
- 3273US9092358B2Memory management unit with pre-filling capabilityRYCHLIK BOHUSLAV·Filed 2012·Granted Jul 28, 2015·4 cites·39 claims
- 3373US7984279B2System and method for using a working global history registerQUALCOMM INC·Filed 2006·Granted Jul 19, 2011·6 cites·18 claims
- 3473US7827392B2Sliding-window, block-based branch target address cacheQUALCOMM INC·Filed 2006·Granted Nov 2, 2010·6 cites·16 claims
- 3573US7093058B2Single request data transfer regardless of size and alignmentIBM·Filed 2005·Granted Aug 15, 2006·6 cites·4 claims
- 3673US6834378B2System on a chip bus with automatic pipeline stage insertion for timing closureIBM·Filed 2002·Granted Dec 21, 2004·15 cites·11 claims
- 3772US8943300B2Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode informationSTEMPEL BRIAN MICHAEL·Filed 2008·Granted Jan 27, 2015·5 cites·17 claims
- 3872US7210024B2Conditional instruction execution via emissary instruction for condition evaluationQUALCOMM INC·Filed 2005·Granted Apr 24, 2007·5 cites·19 claims
- 3971US8782356B2Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regionsPANAVICH JASON LAWRENCE·Filed 2011·Granted Jul 15, 2014·4 cites·34 claims
- 4071US7802055B2Virtually-tagged instruction cache with physically-tagged behaviorQUALCOMM INC·Filed 2006·Granted Sep 21, 2010·5 cites·22 claims
- 4171US7669039B2Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instructionQUALCOMM INC·Filed 2007·Granted Feb 23, 2010·5 cites·19 claims
- 4271US7404042B2Handling cache miss in an instruction crossing a cache line boundaryQUALCOMM INC·Filed 2005·Granted Jul 22, 2008·5 cites·18 claims
- 4371US5809293ASystem and method for program execution tracing within an integrated processorIBM·Filed 1994·Granted Sep 15, 1998·58 cites·29 claims
- 4470US8352682B2Methods and apparatus for issuing memory barrier commands in a weakly ordered storage systemQUALCOMM INC·Filed 2009·Granted Jan 8, 2013·4 cites·22 claims
- 4570US7203826B2Method and apparatus for managing a return stackQUALCOMM INC·Filed 2005·Granted Apr 10, 2007·4 cites·25 claims
- 4670US7035958B2Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the targetIBM·Filed 2002·Granted Apr 25, 2006·15 cites·21 claims
- 4769US7698536B2Method and system for providing an energy efficient register fileQUALCOMM INC·Filed 2005·Granted Apr 13, 2010·4 cites·21 claims
- 4869US7366877B2Speculative instruction issue in a simultaneously multithreaded processorIBM·Filed 2003·Granted Apr 29, 2008·12 cites·14 claims
- 4968US9436616B2Multi-core page table sets of attribute fieldsQUALCOMM INC·Filed 2013·Granted Sep 6, 2016·2 cites·52 claims
- 5068US8145883B2Preloading instructions from an instruction set other than a currently executing instruction setSARTORIUS THOMAS ANDREW·Filed 2010·Granted Mar 27, 2012·2 cites·27 claims
Showing the top 50 of 123 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →