Inventor · disambiguated record
Theodore C. White
Also filed as: WHITE THEODORE · WHITE THEODORE C · WHITE THEODORE CURT
36 granted patents·975 citations·filing 1993–2013
98Inventor score
Top patents by PatentIndex Score
36 records- 0197US6401149B1Methods for context switching within a disk controllerQLOGIC CORP·Filed 2000·Granted Jun 4, 2002·209 cites·21 claims
- 0295US6330626B1Systems and methods for a disk controller memory architectureQLOGIC CORP·Filed 2000·Granted Dec 11, 2001·129 cites·42 claims
- 0394US7865784B1Write validationMARVELL INT LTD·Filed 2006·Granted Jan 4, 2011·26 cites·43 claims
- 0493US8019957B1Method and system for automatic calibration of a DQS signal in a storage controllerMARVELL INT LTD·Filed 2010·Granted Sep 13, 2011·21 cites·18 claims
- 0586US6961877B2System and method for in-line error correction for storage systemsQLOGIC CORP·Filed 2002·Granted Nov 1, 2005·18 cites·13 claims
- 0684US7921243B1System and method for a DDR SDRAM controllerMARVELL INT LTD·Filed 2007·Granted Apr 5, 2011·13 cites·48 claims
- 0781US7286441B1Integrated memory controllerMARVELL INT LTD·Filed 2006·Granted Oct 23, 2007·8 cites·42 claims
- 0880US5511224AConfigurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memoriesUNISYS CORP·Filed 1995·Granted Apr 23, 1996·101 cites·19 claims
- 0979US7007114B1System and method for padding data blocks and/or removing padding from data blocks in storage controllersQLOGIC CORP·Filed 2003·Granted Feb 28, 2006·24 cites·10 claims
- 1079US5386517ADual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speedsUNISYS CORP·Filed 1993·Granted Jan 31, 1995·89 cites·12 claims
- 1177US8122299B2System and method for in-line error correction for storage systemsSI YUJUN·Filed 2005·Granted Feb 21, 2012·3 cites·14 claims
- 1277US7596053B1Integrated memory controllerMARVELL INT LTD·Filed 2006·Granted Sep 29, 2009·6 cites·8 claims
- 1375US8095717B1System and method for configuration register synchronizationWHITE THEODORE C·Filed 2008·Granted Jan 10, 2012·7 cites·20 claims
- 1469US7120084B2Integrated memory controllerMARVELL INT LTD·Filed 2004·Granted Oct 10, 2006·10 cites·5 claims
- 1566US7793063B1Method and system for automatic calibration of a DQS signal in a storage controllerMARVELL INT LTD·Filed 2006·Granted Sep 7, 2010·5 cites·37 claims
- 1663US7287102B1System and method for concatenating dataMARVELL INT LTD·Filed 2004·Granted Oct 23, 2007·9 cites·28 claims
- 1763US5519883AInterbus interface moduleUNISYS CORP·Filed 1993·Granted May 21, 1996·42 cites·15 claims
- 1862US7904656B1Controller for hard disk drive having DWFT (data wedge format table) cache with high-priority initial cache fillMARVELL INT LTD·Filed 2008·Granted Mar 8, 2011·2 cites·21 claims
- 1961US8713224B2System and method for transferring data in storage controllersWHITE THEODORE C·Filed 2005·Granted Apr 29, 2014·2 cites·12 claims
- 2061US8417900B1Power save module for storage controllersPEROZO ANGEL G·Filed 2008·Granted Apr 9, 2013·3 cites·20 claims
- 2161US7535791B1Integrated memory controllerMARVELL INT LTD·Filed 2007·Granted May 19, 2009·1 cites·20 claims
- 2261US7386661B2Power save module for storage controllersMARVELL INT LTD·Filed 2004·Granted Jun 10, 2008·7 cites·52 claims
- 2359US5696937ACache controller utilizing a state machine for controlling invalidations in a network with dual system bussesUNISYS CORP·Filed 1995·Granted Dec 9, 1997·39 cites·6 claims
- 2459US5666515AInformation processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked addressUNISYS CORP·Filed 1996·Granted Sep 9, 1997·38 cites·1 claims
- 2558US8166217B2System and method for reading and writing data using storage controllersWHITE THEODORE C·Filed 2004·Granted Apr 24, 2012·7 cites·20 claims
- 2657US9195538B1System and method for in-line error correction for storage systemsMARVELL INT LTD·Filed 2013·Granted Nov 24, 2015·0 cites·16 claims
- 2756US5845324ADual bus network cache controller system having rapid invalidation cycles and reduced latency for cache accessUNISYS CORP·Filed 1997·Granted Dec 1, 1998·42 cites·4 claims
- 2855US5293621AVarying wait interval retry apparatus and method for preventing bus lockoutUNISYS CORP·Filed 1993·Granted Mar 8, 1994·28 cites·25 claims
- 2953US5809533ADual bus system with multiple processors having data coherency maintenanceUNISYS CORP·Filed 1997·Granted Sep 15, 1998·29 cites·7 claims
- 3052US8402323B2System and method for in-line error correction for storage systemsSI YUJUN·Filed 2012·Granted Mar 19, 2013·0 cites·14 claims
- 3151US9037764B1Method and apparatus for efficiently transferring data in bursts from a storage device to a hostMARVELL INT LTD·Filed 2013·Granted May 19, 2015·0 cites·18 claims
- 3249US5737756ADual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queueUNISYS CORP·Filed 1996·Granted Apr 7, 1998·24 cites·2 claims
- 3342US8572302B1Controller for storage device with improved burst efficiencyWHITE THEODORE·Filed 2007·Granted Oct 29, 2013·0 cites·19 claims
- 3442US5673415AHigh speed two-port interface unit where read commands suspend partially executed write commandsUNISYS CORP·Filed 1996·Granted Sep 30, 1997·20 cites·10 claims
- 3540US5293496AInhibit write apparatus and method for preventing bus lockoutUNISYS CORP·Filed 1993·Granted Mar 8, 1994·12 cites·12 claims
- 3630US5349620ATimer access control apparatusUNISYS CORP·Filed 1993·Granted Sep 20, 1994·1 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →