Inventor · disambiguated record
Tien-I Bao
Also filed as: BAO TIEN-I
253 granted patents·30 pending applications·5,377 citations·filing 1999–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD151TAIWAN SEMICONDUCTOR MFG96YU CHEN-HUA5BAO TIEN I3KO CHUNG-CHI3
Top patents by PatentIndex Score
283 records- 0199US9576814B2Method of spacer patterning to form a target integrated circuit patternTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Feb 21, 2017·3.1k cites·20 claims
- 0299US9153478B2Spacer etching process for integrated circuit designTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Oct 6, 2015·118 cites·20 claims
- 0398US11569124B2Interconnect structure having an etch stop layer over conductive linesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jan 31, 2023·4 cites·20 claims
- 0498US9134633B2System and method for dark field inspectionTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 15, 2015·63 cites·20 claims
- 0598US6181013B1Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured therebyTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Jan 30, 2001·197 cites·18 claims
- 0697US9985134B1FinFETs and methods of forming FinFETsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 29, 2018·18 cites·20 claims
- 0797US9773676B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Sep 26, 2017·17 cites·19 claims
- 0897US9659864B2Method and apparatus for forming self-aligned via with selectively deposited etching stop layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 23, 2017·24 cites·20 claims
- 0997US9312220B2Structure and method for a low-K dielectric with pillar-type air-gapsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Apr 12, 2016·30 cites·25 claims
- 1097US9177797B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 3, 2015·28 cites·20 claims
- 1197US9123776B2Self-aligned double spacer patterning processTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 1, 2015·26 cites·20 claims
- 1296US9041015B2Package structure and methods of forming sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted May 26, 2015·17 cites·21 claims
- 1396US6455417B1Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layerTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Sep 24, 2002·98 cites·15 claims
- 1496US6136680AMethods to improve copper-fluorinated silica glass interconnectsTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Oct 24, 2000·133 cites·35 claims
- 1596US6046108AMethod for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured therebyTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 4, 2000·193 cites·28 claims
- 1695US9941157B2Porogen bonded gap filling material in semiconductor manufacturingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Apr 10, 2018·9 cites·20 claims
- 1795US9036956B2Method of fabricating a polymer waveguideTSENG CHUN-HAO·Filed 2012·Granted May 19, 2015·31 cites·20 claims
- 1895US8652962B2Etch damage and ESL free dual damascene metal interconnectSINGH SUNIL KUMAR·Filed 2012·Granted Feb 18, 2014·23 cites·10 claims
- 1995US7135402B2Sealing pores of low-k dielectrics using CxHyTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Nov 14, 2006·59 cites·16 claims
- 2095US6812043B2Method for forming a carbon doped oxide low-k insulating layerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 2, 2004·82 cites·26 claims
- 2194US10014175B2Lithography using high selectivity spacers for pitch reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jul 3, 2018·7 cites·20 claims
- 2294US9627206B2Method of double patterning lithography process using plurality of mandrels for integrated circuit applicationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Apr 18, 2017·9 cites·20 claims
- 2394US9431297B2Method of forming an interconnect structure for a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Aug 30, 2016·15 cites·20 claims
- 2494US8729703B2Schemes for forming barrier layers for copper in interconnect structuresTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted May 20, 2014·9 cites·20 claims
- 2594US8440564B2Schemes for forming barrier layers for copper in interconnect structuresYU CHEN-HUA·Filed 2012·Granted May 14, 2013·9 cites·20 claims
- 2694US7564136B2Integration scheme for Cu/low-k interconnectsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Jul 21, 2009·31 cites·19 claims
- 2793US10818600B2Structure and method for a low-k dielectric with pillar-type air-gapsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Oct 27, 2020·6 cites·20 claims
- 2893US10312139B2Interconnect structure having an etch stop layer over conductive linesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jun 4, 2019·6 cites·20 claims
- 2993US9922927B2Method and apparatus for forming self-aligned via with selectively deposited etching stop layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Mar 20, 2018·6 cites·20 claims
- 3093US9911646B2Self-aligned double spacer patterning processTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Mar 6, 2018·6 cites·20 claims
- 3193US9786549B2Etch damage and ESL free dual damascene metal interconnectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Oct 10, 2017·6 cites·20 claims
- 3293US9768024B1Multi-layer mask and method of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 19, 2017·7 cites·20 claims
- 3393US9633949B2Copper etching integration schemeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 25, 2017·7 cites·20 claims
- 3493US9136106B2Method for integrated circuit patterningTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 15, 2015·11 cites·20 claims
- 3593US6677251B1Method for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesionTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jan 13, 2004·108 cites·20 claims
- 3692US11411113B2FinFETs and methods of forming FinFETsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 9, 2022·2 cites·20 claims
- 3792US9818690B2Self-aligned interconnection structure and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Nov 14, 2017·9 cites·20 claims
- 3892US9685368B2Interconnect structure having an etch stop layer over conductive linesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jun 20, 2017·6 cites·20 claims
- 3992US9335473B2Package structure and methods of forming sameTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted May 10, 2016·7 cites·20 claims
- 4092US8976833B2Light coupling device and methods of forming sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Mar 10, 2015·11 cites·20 claims
- 4192US6962869B1SiOCH low k surface protection layer formation by CxHy gas plasma treatmentTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 8, 2005·77 cites·26 claims
- 4291US10170306B2Method of double patterning lithography process using plurality of mandrels for integrated circuit applicationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 1, 2019·5 cites·20 claims
- 4391US10164114B2FinFETs and methods of forming FinFETsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 25, 2018·4 cites·20 claims
- 4491US2025357108A1Low-k dielectric and processes for forming same forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4590US9405063B2Integrated metal gratingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Aug 2, 2016·6 cites·20 claims
- 4690US9230911B2Interconnect structure and method of forming the sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jan 5, 2016·9 cites·20 claims
- 4790US7482265B2UV curing of low-k porous dielectricsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Jan 27, 2009·22 cites·19 claims
- 4889US10008382B2Semiconductor device having a porous low-k structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jun 26, 2018·5 cites·20 claims
- 4989US8264066B2Liner formation in 3DIC structuresLO CHING-YU·Filed 2009·Granted Sep 11, 2012·14 cites·13 claims
- 5089US8232201B2Schemes for forming barrier layers for copper in interconnect structuresYU CHEN-HUA·Filed 2011·Granted Jul 31, 2012·5 cites·20 claims
Showing the top 50 of 283 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →