Inventor · disambiguated record
Timothy D. Helvey
Also filed as: HELVEY TIMOTHY D
18 granted patents·1 pending application·37 citations·filing 2008–2015
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
19 records- 0178US8473884B2Slack-based timing budget apportionmentDAEDE RONALD J·Filed 2012·Granted Jun 25, 2013·7 cites·23 claims
- 0276US8949755B2Analyzing sparse wiring areas of an integrated circuit designIBM·Filed 2013·Granted Feb 3, 2015·4 cites·20 claims
- 0374US8250509B2Slack-based timing budget apportionmentDAEDE RONALD J·Filed 2010·Granted Aug 21, 2012·5 cites·25 claims
- 0474US8024683B2Replicating timing data in static timing analysis operationIBM·Filed 2008·Granted Sep 20, 2011·7 cites·13 claims
- 0572US8271923B2Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chipDARSOW CRAIG M·Filed 2010·Granted Sep 18, 2012·4 cites·20 claims
- 0670US8689170B2Changing the location of a buffer bay in a netlistIBM·Filed 2013·Granted Apr 1, 2014·3 cites·14 claims
- 0764US8413104B2Changing the location of a buffer bay in a netlistELLAVSKY MATTHEW R·Filed 2011·Granted Apr 2, 2013·2 cites·6 claims
- 0864US8316333B2Implementing timing pessimism reduction for parallel clock treesDARSOW CRAIG M·Filed 2010·Granted Nov 20, 2012·2 cites·20 claims
- 0962US9223923B2Implementing enhanced physical design quality using historical placement analyticsIBM·Filed 2014·Granted Dec 29, 2015·1 cites·9 claims
- 1062US8819612B1Analyzing timing requirements of a hierarchical integrated circuit designIBM·Filed 2013·Granted Aug 26, 2014·1 cites·20 claims
- 1152US9218445B2Implementing enhanced physical design quality using historical placement analyticsIBM·Filed 2014·Granted Dec 22, 2015·0 cites·11 claims
- 1251US8826214B2Implementing Z directional macro port assignmentIBM·Filed 2013·Granted Sep 2, 2014·0 cites·20 claims
- 1348US7962871B2Concurrently modeling delays between points in static timing analysis operationIBM·Filed 2008·Granted Jun 14, 2011·0 cites·18 claims
- 1446US9087172B2Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macrosIBM·Filed 2013·Granted Jul 21, 2015·0 cites·20 claims
- 1546US8631370B2Swapping ports to change the timing window overlap of adjacent netsBENJAMIN SAMUEL R·Filed 2012·Granted Jan 14, 2014·1 cites·17 claims
- 1645US8448121B2Implementing Z directional macro port assignmentELLAVSKY MATTHEW R·Filed 2011·Granted May 21, 2013·0 cites·21 claims
- 1744US9858380B2Determining positions of storage elements in a logic designIBM·Filed 2015·Granted Jan 2, 2018·0 cites·20 claims
- 1839US8448123B2Implementing net routing with enhanced correlation of pre-buffered and post-buffered routesCURTIS PAUL G·Filed 2010·Granted May 21, 2013·0 cites·17 claims
- 1932US2017169155A1Method to adjust alley gap between large blocks for floorplan optimizationGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →