Inventor · disambiguated record
Tina Wagner
Also filed as: WAGNER TINA · WAGNER TINA J · WAGNER TINA JANE
15 granted patents·1 pending application·334 citations·filing 1997–2012
94Inventor score
Top patents by PatentIndex Score
16 records- 0195US7337420B2Methodology for layout-based modulation and optimization of nitride liner stress effect in compact modelsIBM·Filed 2005·Granted Feb 26, 2008·61 cites·38 claims
- 0291US6930030B2Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thicknessIBM·Filed 2003·Granted Aug 16, 2005·57 cites·20 claims
- 0383US6869542B2Hard mask integrated etch process for patterning of silicon oxide and other dielectric materialsIBM·Filed 2003·Granted Mar 22, 2005·35 cites·17 claims
- 0481US7700425B2Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plugIBM·Filed 2006·Granted Apr 20, 2010·8 cites·16 claims
- 0580US5811357AProcess of etching an oxide layerIBM·Filed 1997·Granted Sep 22, 1998·57 cites·13 claims
- 0677US6345399B1Hard mask process to prevent surface roughness for selective dielectric etchingIBM·Filed 2000·Granted Feb 12, 2002·20 cites·17 claims
- 0774US6387790B1Conversion of amorphous layer produced during IMP Ti depositionIBM·Filed 2000·Granted May 14, 2002·19 cites·19 claims
- 0872US6878624B1Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSiIBM·Filed 2003·Granted Apr 12, 2005·20 cites·20 claims
- 0968US6660664B1Structure and method for formation of a blocked silicide resistorIBM·Filed 2000·Granted Dec 9, 2003·9 cites·22 claims
- 1065US7941780B2Intersect area based ground rule for semiconductor designIBM·Filed 2008·Granted May 10, 2011·2 cites·25 claims
- 1158US6121129AMethod of contact structure formationIBM·Filed 1997·Granted Sep 19, 2000·24 cites·11 claims
- 1256US6436823B1Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formedIBM·Filed 2000·Granted Aug 20, 2002·7 cites·17 claims
- 1350US8631375B2Via selection in integrated circuit designARELT ROBERT R·Filed 2012·Granted Jan 14, 2014·1 cites·20 claims
- 1449US6090722AProcess for fabricating a semiconductor structure having a self-aligned spacerIBM·Filed 1999·Granted Jul 18, 2000·14 cites·19 claims
- 1543US8141027B2Automated sensitivity definition and calibration for design for manufacturing toolsCULP JAMES A·Filed 2010·Granted Mar 20, 2012·0 cites·17 claims
- 1638US2005054169A1Method of manufacture of raised source drain mosfet with top notched gate structure filled with dielectric plug in and device manufactured therebyIBM·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →