Inventor · disambiguated record
Toshiro Akino
Also filed as: AKINO TOSHIRO
12 granted patents·1 pending application·500 citations·filing 1989–2004
93Inventor score
Top patents by PatentIndex Score
13 records- 0189US5852562AMethod and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zonesMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1995·Granted Dec 22, 1998·180 cites·6 claims
- 0270US5187668APlacement optimization system aided by cadMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1990·Granted Feb 16, 1993·59 cites·14 claims
- 0367US6263475B1Method for optimizing component placement in designing a semiconductor device by using a cost valueMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1998·Granted Jul 17, 2001·52 cites·4 claims
- 0465US5468734AProphylactic and remedial preparation for diseases attendant on hyperglycemia, and wholesome foodGODO SHUSEI KK·Filed 1995·Granted Nov 21, 1995·28 cites·5 claims
- 0564US5677249ASemiconductor apparatus and production method for the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1996·Granted Oct 14, 1997·24 cites·6 claims
- 0661US5267177AMethod for VLSI layout pattern compaction by using direct access memoryMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1991·Granted Nov 30, 1993·37 cites·7 claims
- 0753US6292926B1Functional module model, pipelined circuit synthesis and pipelined circuit deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1998·Granted Sep 18, 2001·26 cites·4 claims
- 0847US5159682ASystem for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a redundancy functionMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1989·Granted Oct 27, 1992·52 cites·6 claims
- 0946US5694052AMethod and system for analysis and evaluation of semiconductor circuit performance characteristicMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1996·Granted Dec 2, 1997·15 cites·6 claims
- 1040US5490083AMethod and apparatus for classifying and evaluating logic circuitMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1993·Granted Feb 6, 1996·12 cites·10 claims
- 1136US5757679AMethod and apparatus for modelling MOS transistor characteristics for semiconductor circuit characteristic analysisMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1996·Granted May 26, 1998·12 cites·14 claims
- 1233US2007096219A1Lateral bipolar cmos integrated circuitJURIDICAL FOUNDATION OSAKA IND·Filed 2004·Application pending·0 cites
- 1329US5479657ASystem and method for sorting count information by summing frequencies of usage and using the sums to determine write addressesMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1993·Granted Dec 26, 1995·3 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →