Inventor · disambiguated record
Tolga Ozguner
Also filed as: OZGUNER TOLGA
34 granted patents·5 pending applications·258 citations·filing 2001–2019
96Inventor score
Files withIBM20MICROSOFT TECHNOLOGY LICENSING LLC12BELLOWS MARK DAVID5FAGERNESS GERALD G1IMMING KERRY CHRISTOPHER1
Top patents by PatentIndex Score
39 records- 0197US9978118B1No miss cache structure for real-time image transformations with data compressionMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted May 22, 2018·55 cites·24 claims
- 0289US6910092B2Chip to chip interface for interconnecting chipsIBM·Filed 2001·Granted Jun 21, 2005·60 cites·27 claims
- 0385US9747225B2Interrupt controllerMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2015·Granted Aug 29, 2017·5 cites·20 claims
- 0484US10672368B2No miss cache structure for real-time image transformations with multiple LSR processing enginesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Jun 2, 2020·3 cites·19 claims
- 0583US10242654B2No miss cache structure for real-time image transformationsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Mar 26, 2019·3 cites·19 claims
- 0682US10360832B2Post-rendering image transformation using parallel image transformation pipelinesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Jul 23, 2019·4 cites·20 claims
- 0781US10410349B2Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection powerMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Sep 10, 2019·3 cites·21 claims
- 0881US10255891B2No miss cache structure for real-time image transformations with multiple LSR processing enginesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Apr 9, 2019·3 cites·21 claims
- 0978US7467277B2Memory controller operating in a system with a variable system clockIBM·Filed 2006·Granted Dec 16, 2008·8 cites·9 claims
- 1076US7757040B2Memory command and address conversion between an XDR interface and a double data rate interfaceIBM·Filed 2007·Granted Jul 13, 2010·8 cites·22 claims
- 1174US10241470B2No miss cache structure for real-time image transformations with data compressionMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2018·Granted Mar 26, 2019·1 cites·23 claims
- 1274US7224701B2Method and apparatus for implementing frame header alterations using byte-wise arithmetic logic unitsIBM·Filed 2002·Granted May 29, 2007·20 cites·15 claims
- 1374US7218647B2Method and apparatus for implementing frame header alterationsIBM·Filed 2002·Granted May 15, 2007·20 cites·17 claims
- 1472US7239635B2Method and apparatus for implementing alterations on multiple concurrent framesIBM·Filed 2002·Granted Jul 3, 2007·17 cites·18 claims
- 1571US7761682B2Memory controller operating in a system with a variable system clockIBM·Filed 2008·Granted Jul 20, 2010·4 cites·10 claims
- 1668US6996650B2Method and apparatus for implementing multiple configurable sub-busses of a point-to-point busIBM·Filed 2002·Granted Feb 7, 2006·14 cites·20 claims
- 1765US10403029B2Methods and systems for multistage post-rendering image transformationMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Sep 3, 2019·1 cites·20 claims
- 1864US6880026B2Method and apparatus for implementing chip-to-chip interconnect bus initializationIBM·Filed 2002·Granted Apr 12, 2005·11 cites·16 claims
- 1960US7752379B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2009·Granted Jul 6, 2010·1 cites·8 claims
- 2059US8219745B2Memory controller to utilize DRAM write buffersBELLOWS MARK DAVID·Filed 2004·Granted Jul 10, 2012·11 cites·20 claims
- 2154US10338816B2Reducing negative effects of insufficient data throughput for real-time processingMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2018·Granted Jul 2, 2019·0 cites·20 claims
- 2254US7757006B2Implementing conditional packet alterations based on transmit portIBM·Filed 2008·Granted Jul 13, 2010·0 cites·8 claims
- 2352US10095408B2Reducing negative effects of insufficient data throughput for real-time processingMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Oct 9, 2018·0 cites·20 claims
- 2452US7487318B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2007·Granted Feb 3, 2009·0 cites·4 claims
- 2548US7475161B2Implementing conditional packet alterations based on transmit portIBM·Filed 2003·Granted Jan 6, 2009·0 cites·4 claims
- 2648US7380052B2Reuse of functional data buffers for pattern buffers in XDR DRAMIBM·Filed 2004·Granted May 27, 2008·4 cites·8 claims
- 2748US7330478B2Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processorIBM·Filed 2003·Granted Feb 12, 2008·0 cites·5 claims
- 2848US7321950B2Method and apparatus for managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2005·Granted Jan 22, 2008·0 cites·14 claims
- 2948US7225097B2Methods and apparatus for memory calibrationIBM·Filed 2005·Granted May 29, 2007·2 cites·20 claims
- 3046US8170024B2Implementing pointer and stake model for frame alteration code in a network processorIMMING KERRY CHRISTOPHER·Filed 2007·Granted May 1, 2012·0 cites·13 claims
- 3142US10514753B2Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection powerMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Dec 24, 2019·0 cites·25 claims
- 3242US7669028B2Optimizing data bandwidth across a variable asynchronous clock domainIBM·Filed 2006·Granted Feb 23, 2010·0 cites·20 claims
- 3342US2007220361A1Method and apparatus for guaranteeing memory bandwidth for trace dataIBM·Filed 2006·Application pending·0 cites
- 3441US7925823B2Reuse of functional data buffers for pattern buffers in XDR DRAMIBM·Filed 2007·Granted Apr 12, 2011·0 cites·6 claims
- 3540US2008183916A1Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 3640US2008168206A1Methods and Apparatus for Interfacing a Processor and a MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 3740US2008168262A1Methods and Apparatus for Software Control of a Non-Functional Operation on MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 3836US8213428B2Methods and apparatus for indexing memory of a network processorFAGERNESS GERALD G·Filed 2003·Granted Jul 3, 2012·0 cites·15 claims
- 3930US2008168298A1Methods and Apparatus for Calibrating Heterogeneous Memory InterfacesBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →