Inventor · disambiguated record
Tonia M. Rose
Also filed as: ROSE TONIA M
1 granted patent·8 pending applications·0 citations·filing 2022–2024
6Inventor score
Files withINTEL CORP9
Top patents by PatentIndex Score
9 records- 0148US12470231B2Method and apparatus to perform cyclic redundancy check training in a memory moduleINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·20 claims
- 0248US2024241842A1Accelerated dram (dynamic random access memory) trainingINTEL CORP·Filed 2024·Application pending·0 cites
- 0347US2023136268A1Autonomous backside data buffer to memory chip write training controlINTEL CORP·Filed 2022·Application pending·0 cites
- 0446US2023214669A1Hybrid search to train memory and high-speed input/output interfacesINTEL CORP·Filed 2023·Application pending·0 cites
- 0545US2022276958A1Apparatus and method for per memory chip addressingINTEL CORP·Filed 2022·Application pending·0 cites
- 0644US2024345969A1Dynamically insert timing and voltage offset control (voc) offsets in input/output (io) during functional trafficINTEL CORP·Filed 2024·Application pending·0 cites
- 0741US2023125412A1Autonomous dimm write leveling trainingINTEL CORP·Filed 2022·Application pending·0 cites
- 0840US2023385208A1Accelerated memory training through in-band configuration register update modeINTEL CORP·Filed 2023·Application pending·0 cites
- 0939US2022300197A1Autonomous backside chip select (cs) and command/address (ca) training modesINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →