Inventor · disambiguated record
Toshiyuki Sadakane
Also filed as: SADAKANE TOSHIYUKI
2 granted patents·1 pending application·6 citations·filing 2005–2008
53Inventor score
Technology areasG06F
Top patents by PatentIndex Score
3 records- 0164US7418688B2Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuitRENESAS TECH CORP·Filed 2005·Granted Aug 26, 2008·3 cites·6 claims
- 0258US8108809B2Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuitSADAKANE TOSHIYUKI·Filed 2008·Granted Jan 31, 2012·3 cites·4 claims
- 0338US2009019404A1Method for calculating difficulty level of routing in netlistRENESAS TECH CORP·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →