Inventor · disambiguated record
Trevor J. Bauer
Also filed as: BAPAT SHEKHAR · BAUER TREVOR · BAUER TREVOR J
73 granted patents·1 pending application·4,109 citations·filing 1996–2023
99Inventor score
Top patents by PatentIndex Score
74 records- 0199US7965102B1Formation of columnar application specific circuitry using a columnar programmable deviceXILINX INC·Filed 2008·Granted Jun 21, 2011·188 cites·18 claims
- 0299US6529040B1FPGA lookup table with speed read decoderXILINX INC·Filed 2000·Granted Mar 4, 2003·241 cites·21 claims
- 0399US6526557B1Architecture and method for partially reconfiguring an FPGAXILINX INC·Filed 2000·Granted Feb 25, 2003·196 cites·25 claims
- 0499US6448808B2Interconnect structure for a programmable logic deviceXILINX INC·Filed 2001·Granted Sep 10, 2002·225 cites·23 claims
- 0599US5914616AFPGA repeatable interconnect structure with hierarchical interconnect linesXILINX INC·Filed 1997·Granted Jun 22, 1999·495 cites·39 claims
- 0698US6956399B1High-speed lookup table circuits and methods for programmable logic devicesXILINX INC·Filed 2004·Granted Oct 18, 2005·137 cites·61 claims
- 0797US7218139B1Programmable integrated circuit providing efficient implementations of arithmetic functionsXILINX INC·Filed 2005·Granted May 15, 2007·68 cites·20 claims
- 0897US7202698B1Integrated circuit having a programmable input structure with bounce capabilityXILINX INC·Filed 2005·Granted Apr 10, 2007·47 cites·20 claims
- 0997US5963050AConfigurable logic element with fast feedback pathsXILINX INC·Filed 1997·Granted Oct 5, 1999·129 cites·13 claims
- 1096US6759869B1Large crossbar switch implemented in FPGAXILINX INC·Filed 2002·Granted Jul 6, 2004·83 cites·24 claims
- 1196US5920202AConfigurable logic element with ability to evaluate five and six input functionsXILINX INC·Filed 1997·Granted Jul 6, 1999·121 cites·11 claims
- 1296US5889413ALookup tables which double as shift registersXILINX INC·Filed 1996·Granted Mar 30, 1999·108 cites·13 claims
- 1395US7196543B1Integrated circuit having a programmable input structure with optional fanout capabilityXILINX INC·Filed 2005·Granted Mar 27, 2007·32 cites·20 claims
- 1495US6204689B1Input/output interconnect circuit for FPGAsXILINX INC·Filed 1999·Granted Mar 20, 2001·115 cites·21 claims
- 1594US7057413B1Large crossbar switch implemented in FPGAXILINX INC·Filed 2004·Granted Jun 6, 2006·65 cites·24 claims
- 1694US6288568B1FPGA architecture with deep look-up table RAMsXILINX INC·Filed 2000·Granted Sep 11, 2001·57 cites·16 claims
- 1794US6204690B1FPGA architecture with offset interconnect linesXILINX INC·Filed 2000·Granted Mar 20, 2001·45 cites·11 claims
- 1894US6107826AInterconnect structure for FPGA with configurable delay locked loopXILINX INC·Filed 1998·Granted Aug 22, 2000·94 cites·19 claims
- 1993US7215138B1Programmable lookup table with dual input and output terminals in shift register modeXILINX INC·Filed 2005·Granted May 8, 2007·25 cites·20 claims
- 2093US6323682B1FPGA architecture with wide function multiplexersXILINX INC·Filed 2000·Granted Nov 27, 2001·53 cites·10 claims
- 2193US6107827AFPGA CLE with two independent carry chainsXILINX INC·Filed 1999·Granted Aug 22, 2000·59 cites·8 claims
- 2293US5942913AFPGA repeatable interconnect structure with bidirectional and unidirectional interconnect linesXILINX INC·Filed 1997·Granted Aug 24, 1999·91 cites·9 claims
- 2393US5844844AFPGA memory element programmably triggered on both clock edgesXILINX INC·Filed 1997·Granted Dec 1, 1998·99 cites·30 claims
- 2492US10963411B1Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archetureXILINX INC·Filed 2019·Granted Mar 30, 2021·8 cites·20 claims
- 2592US7345507B1Multi-product die configurable as two or more programmable integrated circuits of different logic capacitiesXILINX INC·Filed 2006·Granted Mar 18, 2008·27 cites·20 claims
- 2692US6621296B2FPGA lookup table with high speed read decorderXILINX INC·Filed 2002·Granted Sep 16, 2003·37 cites·11 claims
- 2792US5907248AFPGA interconnect structure with high-speed high fanout capabilityXILINX INC·Filed 1998·Granted May 25, 1999·70 cites·18 claims
- 2891US7375552B1Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structureXILINX INC·Filed 2005·Granted May 20, 2008·26 cites·11 claims
- 2991US7312631B1Structures and methods for avoiding hold time violations in a programmable logic deviceXILINX INC·Filed 2005·Granted Dec 25, 2007·18 cites·8 claims
- 3091US6907595B2Partial reconfiguration of a programmable logic device using an on-chip processorXILINX INC·Filed 2002·Granted Jun 14, 2005·91 cites·19 claims
- 3191US6864715B1Windowing circuit for aligning data and clock signalsXILINX INC·Filed 2003·Granted Mar 8, 2005·47 cites·10 claims
- 3291US6292022B2Interconnect structure for a programmable logic deviceXILINX INC·Filed 2001·Granted Sep 18, 2001·31 cites·23 claims
- 3391US6124731AConfigurable logic element with ability to evaluate wide logic functionsXILINX INC·Filed 2000·Granted Sep 26, 2000·37 cites·6 claims
- 3490US8001511B1Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC diesXILINX INC·Filed 2008·Granted Aug 16, 2011·16 cites·9 claims
- 3590US7402443B1Methods of providing families of integrated circuits with similar dies partially disabled using product selection codesXILINX INC·Filed 2006·Granted Jul 22, 2008·20 cites·20 claims
- 3690US7265576B1Programmable lookup table with dual input and output terminals in RAM modeXILINX INC·Filed 2005·Granted Sep 4, 2007·19 cites·18 claims
- 3789US8058905B1Clock distribution to facilitate gated clocksKLEIN MATTHEW H·Filed 2009·Granted Nov 15, 2011·23 cites·16 claims
- 3889US6798241B1Methods for aligning data and clock signalsXILINX INC·Filed 2003·Granted Sep 28, 2004·39 cites·19 claims
- 3989US6297665B1FPGA architecture with dual-port deep look-up table RAMSXILINX INC·Filed 2000·Granted Oct 2, 2001·50 cites·12 claims
- 4089US5627480ATristatable bidirectional buffer for tristate bus linesXILINX INC·Filed 1996·Granted May 6, 1997·63 cites·4 claims
- 4188US8933447B1Method and apparatus for programmable device testing in stacked die applicationsRAHMAN ARIFUR·Filed 2010·Granted Jan 13, 2015·10 cites·15 claims
- 4288US6051992AConfigurable logic element with ability to evaluate five and six input functionsXILINX INC·Filed 1999·Granted Apr 18, 2000·44 cites·4 claims
- 4386US6373279B1FPGA lookup table with dual ended writes for ram and shift register modesXILINX INC·Filed 2000·Granted Apr 16, 2002·31 cites·8 claims
- 4486US6346825B1Block RAM with configurable data width and parity for use in a field programmable gate arrayXILINX INC·Filed 2000·Granted Feb 12, 2002·29 cites·23 claims
- 4586US6262597B1FIFO in FPGA having logic elements that include cascadable shift registersXILINX INC·Filed 2000·Granted Jul 17, 2001·26 cites·4 claims
- 4686US5724276ALogic block structure optimized for sum generationXILINX INC·Filed 1996·Granted Mar 3, 1998·134 cites·3 claims
- 4785US8937491B2Clock network architectureXILINX INC·Filed 2012·Granted Jan 20, 2015·8 cites·19 claims
- 4885US6118298AStructure for optionally cascading shift registersXILINX INC·Filed 1999·Granted Sep 12, 2000·50 cites·7 claims
- 4984US7451421B1Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC diesXILINX INC·Filed 2006·Granted Nov 11, 2008·12 cites·8 claims
- 5083US6232845B1Circuit for measuring signal delays in synchronous memory elementsXILINX INC·Filed 1999·Granted May 15, 2001·49 cites·22 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →