Inventor · disambiguated record
Trung Diep
Also filed as: DIEP TRUNG · DIEP TRUNG A · DIEP TRUNG AM
27 granted patents·2 pending applications·107 citations·filing 1999–2024
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
29 records- 0187US8010969B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2005·Granted Aug 30, 2011·16 cites·32 claims
- 0284US12222871B2Methods and apparatuses for addressing memory cachesRAMBUS INC·Filed 2024·Granted Feb 11, 2025·0 cites·20 claims
- 0384US10891241B2Cache memory that supports tagless addressingRAMBUS INC·Filed 2018·Granted Jan 12, 2021·2 cites·20 claims
- 0481US8205200B2Compiler-based scheduling optimization hints for user-level threadsLIAO SHIH-WEI·Filed 2005·Granted Jun 19, 2012·13 cites·24 claims
- 0578US11921642B2Methods and apparatuses for addressing memory cachesRAMBUS INC·Filed 2022·Granted Mar 5, 2024·0 cites·20 claims
- 0678US7810083B2Mechanism to emulate user-level multithreading on an OS-sequestered sequencerINTEL CORP·Filed 2004·Granted Oct 5, 2010·25 cites·37 claims
- 0777US12124382B2Cache memory that supports tagless addressingRAMBUS INC·Filed 2022·Granted Oct 22, 2024·0 cites·20 claims
- 0874US9465961B2Methods and circuits for securing proprietary memory transactionsRAMBUS INC·Filed 2013·Granted Oct 11, 2016·3 cites·7 claims
- 0972US11500781B2Methods and apparatuses for addressing memory cachesRAMBUS INC·Filed 2020·Granted Nov 15, 2022·0 cites·20 claims
- 1071US9262342B2Process authenticated memory page encryptionRAMBUS INC·Filed 2013·Granted Feb 16, 2016·2 cites·19 claims
- 1170US11537531B2Cache memory that supports tagless addressingRAMBUS INC·Filed 2020·Granted Dec 27, 2022·0 cites·20 claims
- 1268US8887174B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersHANKINS RICHARD A·Filed 2011·Granted Nov 11, 2014·2 cites·10 claims
- 1367US11176037B2Wear leveling in a memory systemRAMBUS INC·Filed 2019·Granted Nov 16, 2021·0 cites·20 claims
- 1466US10133676B2Cache memory that supports tagless addressingZHENG HONGZHONG·Filed 2011·Granted Nov 20, 2018·1 cites·23 claims
- 1566US9390025B2Wear leveling in a memory systemRAMBUS INC·Filed 2012·Granted Jul 12, 2016·1 cites·20 claims
- 1665US10853261B2Methods and apparatuses for addressing memory cachesRAMBUS INC·Filed 2018·Granted Dec 1, 2020·0 cites·20 claims
- 1765US9069605B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionINTEL CORP·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 1864US10037433B2Secure text retrievalNTT DOCOMO INC·Filed 2015·Granted Jul 31, 2018·1 cites·20 claims
- 1963US9442838B2Remapping memory cells based on future endurance measurementsRAMBUS INC·Filed 2013·Granted Sep 13, 2016·1 cites·21 claims
- 2060US10515010B2Wear leveling in a memory systemRAMBUS INC·Filed 2018·Granted Dec 24, 2019·0 cites·20 claims
- 2160US10102140B2Methods and apparatuses for addressing memory cachesRAMBUS INC·Filed 2016·Granted Oct 16, 2018·0 cites·20 claims
- 2259US6330646B1Arbitration mechanism for a computer system having a unified memory architectureINTEL CORP·Filed 1999·Granted Dec 11, 2001·36 cites·23 claims
- 2356US9934142B2Wear leveling in a memory systemRAMBUS INC·Filed 2016·Granted Apr 3, 2018·0 cites·20 claims
- 2454US9734357B2Process authenticated memory page encryptionRAMBUS INC·Filed 2016·Granted Aug 15, 2017·0 cites·20 claims
- 2553US8607235B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionHANKINS RICHARD A·Filed 2004·Granted Dec 10, 2013·3 cites·34 claims
- 2649US9569359B2Methods and apparatuses for addressing memory cachesDIEP TRUNG·Filed 2012·Granted Feb 14, 2017·0 cites·20 claims
- 2742US2004049666A1Method and apparatus for variable pop hardware return address stackFiled 2002·Application pending·0 cites
- 2841US8935489B2Adaptively time-multiplexing memory references from multiple processor coresWOO STEVEN C·Filed 2010·Granted Jan 13, 2015·0 cites·36 claims
- 2940US2007074217A1Scheduling optimizations for user-level threadsRAKVIC RYAN·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →