Inventor · disambiguated record
Tracy J. Feist
Also filed as: FEIST TRACY J
3 granted patents·2 pending applications·2 citations·filing 2010–2024
51Inventor score
Top patents by PatentIndex Score
5 records- 0171US10644680B1Application of duty cycle correction to a level shifter via a feedback common mode resistorADVANCED MICRO DEVICES INC·Filed 2019·Granted May 5, 2020·2 cites·20 claims
- 0259US12034440B2Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed linksADVANCED MICRO DEVICES INC·Filed 2021·Granted Jul 9, 2024·0 cites·20 claims
- 0358US2025007516A1Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed linksADVANCED MICRO DEVICES INC·Filed 2024·Application pending·0 cites
- 0446US2014070849A1Methods and structure for on-chip clock jitter testing and analysisLSI CORP·Filed 2013·Application pending·0 cites
- 0534US8619935B2Methods and structure for on-chip clock jitter testing and analysisFEIST DOUGLAS J·Filed 2010·Granted Dec 31, 2013·0 cites·12 claims
Join the waitlist — get patent alerts
Get an alert when Tracy J. Feist files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →