Inventor · disambiguated record
Tryggve Fossum
Also filed as: FOSSUM TRYGGVE
42 granted patents·4 pending applications·2,595 citations·filing 1983–2016
99Inventor score
Files withDIGITAL EQUIPMENT CORP24INTEL CORP10FOSSUM TRYGGVE3CHEE NICHOLAS CHENG HWA1COMPAQ INFORMATION TECHNOLOGIE1
Top patents by PatentIndex Score
46 records- 0196US5142634ABranch predictionDIGITAL EQUIPMENT CORP·Filed 1989·Granted Aug 25, 1992·276 cites·47 claims
- 0295US7392414B2Method, system, and apparatus for improving multi-core processor performanceINTEL CORP·Filed 2006·Granted Jun 24, 2008·39 cites·15 claims
- 0395US6493741B1Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unitCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Dec 10, 2002·211 cites·60 claims
- 0494US6675192B2Temporary halting of thread execution until monitoring of armed events to memory location identified in working registersHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 6, 2004·92 cites·5 claims
- 0593US4888679AMethod and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elementsDIGITAL EQUIPMENT CORP·Filed 1988·Granted Dec 19, 1989·151 cites·31 claims
- 0690US5155854ASystem for arbitrating communication requests using multi-pass control unit based on availability of system resourcesDIGITAL EQUIPMENT CORP·Filed 1989·Granted Oct 13, 1992·134 cites·6 claims
- 0790US4985825ASystem for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computerDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jan 15, 1991·128 cites·11 claims
- 0889US9294419B2Scalable multi-layer 2D-mesh routersINTEL CORP·Filed 2013·Granted Mar 22, 2016·12 cites·30 claims
- 0989US5222224AScheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted Jun 22, 1993·163 cites·4 claims
- 1089US5067069AControl of multiple functional units with parallel operation in a microcoded execution unitDIGITAL EQUIPMENT CORP·Filed 1989·Granted Nov 19, 1991·113 cites·20 claims
- 1188US5222223AMethod and apparatus for ordering and queueing multiple memory requestsDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jun 22, 1993·100 cites·9 claims
- 1287US7389440B2Method, system, and apparatus for improving multi-core processor performanceINTEL CORP·Filed 2006·Granted Jun 17, 2008·13 cites·14 claims
- 1387US5175837ASynchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bitsDIGITAL EQUIPMENT CORP·Filed 1989·Granted Dec 29, 1992·112 cites·8 claims
- 1487US5109495AMethod and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processorDIGITAL EQUIPMENT CORP·Filed 1989·Granted Apr 28, 1992·105 cites·19 claims
- 1586US5125083AMethod and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer systemDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jun 23, 1992·91 cites·16 claims
- 1683US4982402AMethod and apparatus for detecting and correcting errors in a pipelined computer systemDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jan 1, 1991·84 cites·18 claims
- 1783US4742451AInstruction prefetch system for conditional branch instruction for central processor unitDIGITAL EQUIPMENT CORP·Filed 1984·Granted May 3, 1988·72 cites·16 claims
- 1882US7788519B2Method, system, and apparatus for improving multi-core processor performanceINTEL CORP·Filed 2007·Granted Aug 31, 2010·8 cites·6 claims
- 1981US10402168B2Low energy consumption mantissa multiplication for floating point multiply-add operationsINTEL CORP·Filed 2016·Granted Sep 3, 2019·3 cites·24 claims
- 2081US9317263B2Hardware compilation and/or translation with fault detection and roll back functionalityINTEL CORP·Filed 2014·Granted Apr 19, 2016·6 cites·28 claims
- 2181US4995041AWrite back buffer with error correcting capabilitiesDIGITAL EQUIPMENT CORP·Filed 1989·Granted Feb 19, 1991·68 cites·17 claims
- 2280US5285323AIntegrated circuit chip having primary and secondary random access memories for a hierarchical cacheDIGITAL EQUIPMENT CORP·Filed 1993·Granted Feb 8, 1994·96 cites·16 claims
- 2380US5168573AMemory device for storing vector registersDIGITAL EQUIPMENT CORP·Filed 1989·Granted Dec 1, 1992·41 cites·11 claims
- 2478US8190863B2Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restrictionFOSSUM TRYGGVE·Filed 2004·Granted May 29, 2012·24 cites·5 claims
- 2578US5148528AMethod and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable lengthDIGITAL EQUIPMENT CORP·Filed 1989·Granted Sep 15, 1992·59 cites·31 claims
- 2676US5113521AMethod and apparatus for handling faults of vector instructions causing memory management exceptionsDIGITAL EQUIPMENT CORP·Filed 1991·Granted May 12, 1992·79 cites·25 claims
- 2774US5142631ASystem for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose registerDIGITAL EQUIPMENT CORP·Filed 1989·Granted Aug 25, 1992·54 cites·27 claims
- 2871US8769201B2Technique for controlling computing resourcesHASENPLAUGH WILLIAM·Filed 2008·Granted Jul 1, 2014·7 cites·28 claims
- 2969US4949250AMethod and apparatus for executing instructions for a vector processing systemDIGITAL EQUIPMENT CORP·Filed 1988·Granted Aug 14, 1990·40 cites·13 claims
- 3068US5349651ASystem for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translationDIGITAL EQUIPMENT CORP·Filed 1991·Granted Sep 20, 1994·51 cites·16 claims
- 3168US4980817AVector register system for executing plural read/write commands concurrently and independently routing data to plural read/write portsDIGITAL EQUIPMENT·Filed 1987·Granted Dec 25, 1990·42 cites·19 claims
- 3267US8799902B2Priority based throttling for power/performance quality of serviceILLIKKAL RAMESH KUMAR·Filed 2007·Granted Aug 5, 2014·6 cites·19 claims
- 3366US7380169B2Converting merge buffer system-kill errors to process-kill errorsINTEL CORP·Filed 2004·Granted May 27, 2008·12 cites·20 claims
- 3464US9250682B2Distributed power management for multi-core processorsINTEL CORP·Filed 2012·Granted Feb 2, 2016·1 cites·22 claims
- 3560US8924690B2Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restrictionFOSSUM TRYGGVE·Filed 2012·Granted Dec 30, 2014·1 cites·20 claims
- 3660US5829051AApparatus and method for intelligent multiple-probe cache allocationDIGITAL EQUIPMENT CORP·Filed 1994·Granted Oct 27, 1998·33 cites·17 claims
- 3759US4994996APipelined floating point adder for digital computerDIGITAL EQUIPMENT CORP·Filed 1989·Granted Feb 19, 1991·29 cites·35 claims
- 3858US4583222AMethod and apparatus for self-testing of floating point accelerator processorsDIGITAL EQUIPMENT CORP·Filed 1983·Granted Apr 15, 1986·27 cites·11 claims
- 3956US7370231B2Method of handling errorsINTEL CORP·Filed 2004·Granted May 6, 2008·5 cites·24 claims
- 4055US8893094B2Hardware compilation and/or translation with fault detection and roll back functionalityCHEE NICHOLAS CHENG HWA·Filed 2011·Granted Nov 18, 2014·1 cites·30 claims
- 4146US8244980B2Shared cache performanceFOSSUM TRYGGVE·Filed 2006·Granted Aug 14, 2012·0 cites·31 claims
- 4246US2005050310A1Method, system, and apparatus for improving multi-core processor performanceFiled 2003·Application pending·0 cites
- 4346US2004073905A1Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unitFiled 2003·Application pending·0 cites
- 4443US2006212677A1Multicore processor having active and inactive execution coresINTEL CORP·Filed 2005·Application pending·0 cites
- 4536US2012246407A1Method and system to improve unaligned cache memory accessesHASENPLAUGH WILLIAM C·Filed 2011·Application pending·0 cites
- 4629US5093775AMicrocode control system for digital data processing systemDIGITAL EQUIPMENT CORP·Filed 1983·Granted Mar 3, 1992·6 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →