Inventor · disambiguated record
Trevor Garner
Also filed as: GARNER TREVOR · GARNER TREVOR S · GARNER TREVOR SCOTT
14 granted patents·1 pending application·631 citations·filing 1997–2006
94Inventor score
Top patents by PatentIndex Score
15 records- 0196US6757768B1Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network nodeCISCO TECH IND·Filed 2001·Granted Jun 29, 2004·184 cites·51 claims
- 0294US7411957B2Hardware filtering support for denial-of-service attacksCISCO TECH INC·Filed 2004·Granted Aug 12, 2008·134 cites·25 claims
- 0393US6832279B1Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network nodeCISCO TECH INC·Filed 2001·Granted Dec 14, 2004·94 cites·26 claims
- 0483US7124231B1Split transaction reordering circuitCISCO TECH INC·Filed 2002·Granted Oct 17, 2006·40 cites·52 claims
- 0582US7346059B1Header range check hash circuitCISCO TECH INC·Filed 2003·Granted Mar 18, 2008·39 cites·21 claims
- 0679US7174394B1Multi processor enqueue packet circuitCISCO TECH INC·Filed 2002·Granted Feb 6, 2007·29 cites·44 claims
- 0777US6708258B1Computer system for eliminating memory read-modify-write operations during packet transfersCISCO TECH IND·Filed 2001·Granted Mar 16, 2004·25 cites·26 claims
- 0875US7302548B1System and method for communicating in a multi-processor environmentCISCO TECH INC·Filed 2002·Granted Nov 27, 2007·21 cites·28 claims
- 0971US7155576B1Pre-fetching and invalidating packet information in a cache memoryCISCO TECH INC·Filed 2003·Granted Dec 26, 2006·17 cites·39 claims
- 1068US8010966B2Multi-threaded processing using path locksCISCO TECH INC·Filed 2006·Granted Aug 30, 2011·5 cites·20 claims
- 1161US6192486B1Memory defect steering circuitIBM·Filed 1998·Granted Feb 20, 2001·19 cites·41 claims
- 1259US8228908B2Apparatus for hardware-software classification of data packet flowsGARNER TREVOR·Filed 2006·Granted Jul 24, 2012·4 cites·31 claims
- 1355US8453147B2Techniques for reducing thread overhead for systems with multiple multi-threaded processorsJETER ROBERT·Filed 2006·Granted May 28, 2013·2 cites·18 claims
- 1449US6001662AMethod and system for providing a reusable configurable self-test controller for manufactured integrated circuitsIBM·Filed 1997·Granted Dec 14, 1999·18 cites·22 claims
- 1543US2005171937A1Memory efficient hashing algorithmFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →