Inventor · disambiguated record
Tseng Chin Lo
Also filed as: LO TSENG CHIN
16 granted patents·1 pending application·119 citations·filing 2000–2023
92Inventor score
Top patents by PatentIndex Score
17 records- 0193US10283496B2Integrated circuit filler and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 7, 2019·10 cites·20 claims
- 0291US10679980B2Integrated circuit filler and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 9, 2020·5 cites·20 claims
- 0390US11762302B2Integrated circuit overlay test patterns and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 19, 2023·2 cites·20 claims
- 0489US11309307B2Integrated circuit filler and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Apr 19, 2022·2 cites·20 claims
- 0589US6323097B1Electrical overlay/spacing monitor method using a ladder resistorTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Nov 27, 2001·61 cites·35 claims
- 0688US10161965B2Method of test probe alignment controlTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Dec 25, 2018·6 cites·20 claims
- 0787US10388645B2Integrated circuit filler and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Aug 20, 2019·3 cites·20 claims
- 0884US12183729B2Integrated circuit filler and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Dec 31, 2024·0 cites·20 claims
- 0982US7934173B2Reverse dummy insertion algorithmTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Apr 26, 2011·16 cites·18 claims
- 1079US7782073B2High accuracy and universal on-chip switch matrix testlineTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Aug 24, 2010·11 cites·18 claims
- 1178US11776948B2Integrated circuit filler and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Oct 3, 2023·0 cites·20 claims
- 1276US12271116B2Method of measuring mask overlay using test patternsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Apr 8, 2025·0 cites·20 claims
- 1367US9000798B2Method of test probe alignment controlCHEN JUI-LONG·Filed 2012·Granted Apr 7, 2015·2 cites·20 claims
- 1459US9995770B2Multidirectional semiconductor arrangement testingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jun 12, 2018·1 cites·20 claims
- 1556US11016398B2Integrated circuit overlay test patterns and method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 25, 2021·0 cites·20 claims
- 1645US7825678B2Test pad design for reducing the effect of contact resistancesTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Nov 2, 2010·0 cites·12 claims
- 1742US2008244475A1Network based integrated circuit testline generatorLO TSENG CHIN·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →