Inventor · disambiguated record
Tsengyou Syau
Also filed as: SYAU TSENGYOU
8 granted patents·1 pending application·183 citations·filing 1999–2013
89Inventor score
Top patents by PatentIndex Score
9 records- 0193US7582567B1Method for forming CMOS device with self-aligned contacts and region formed using salicide processINTEGRATED DEVICE TECH·Filed 2006·Granted Sep 1, 2009·26 cites·20 claims
- 0288US7037774B1Self-aligned contact structure and process for forming self-aligned contact structureINTEGRATED DEVICE TECH·Filed 2004·Granted May 2, 2006·57 cites·16 claims
- 0381US6534414B1Dual-mask etch of dual-poly gate in CMOS processingINTEGRATED DEVICE TECH·Filed 2000·Granted Mar 18, 2003·33 cites·31 claims
- 0479US7098114B1Method for forming cmos device with self-aligned contacts and region formed using salicide processINTEGRATED DEVICE TECH·Filed 2004·Granted Aug 29, 2006·22 cites·9 claims
- 0573US6566236B1Gate structures with increased etch margin for self-aligned contact and the method of forming the sameINTEGRATED DEVICE TECH·Filed 2000·Granted May 20, 2003·16 cites·28 claims
- 0669US7125783B2Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet cleanINTEGRATED DEVICE TECH·Filed 2001·Granted Oct 24, 2006·14 cites·20 claims
- 0753US7125775B1Method for forming hybrid device gatesINTEGRATED DEVICE TECH·Filed 2004·Granted Oct 24, 2006·5 cites·12 claims
- 0842US2015048514A1Stacked via structures and methods of fabricationQUALCOMM MEMS TECHNOLOGIES INC·Filed 2013·Application pending·0 cites
- 0938US6306771B1Process for preventing the formation of ring defectsINTEGRATED DEVICE TECH·Filed 1999·Granted Oct 23, 2001·10 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →