Inventor · disambiguated record
Tse-Hsien Wang
Also filed as: WANG TSE-HSIEN
8 granted patents·2 pending applications·118 citations·filing 1999–2008
86Inventor score
Top patents by PatentIndex Score
10 records- 0184US7020834B2Circuit and signal encoding method for reducing the number of serial ATA external PHY signalsVIA TECH INC·Filed 2002·Granted Mar 28, 2006·48 cites·15 claims
- 0264US6678756B1Method for controlling a first-in-first-out array to facilitate data transmissions between a lower frequency domain and a higher frequency domain of a computer systemVIA TECH INC·Filed 2000·Granted Jan 13, 2004·18 cites·32 claims
- 0360US7085861B2Serial ATA control circuit for automatically switching connection pathVIA TECH INC·Filed 2003·Granted Aug 1, 2006·9 cites·9 claims
- 0458US7159055B2Physical layer apparatus compliant to serial and parallel ATA interfacesVIA TECH INC·Filed 2003·Granted Jan 2, 2007·8 cites·10 claims
- 0552US6549964B1Delayed transaction method and device used in a PCI systemVIA TECH INC·Filed 1999·Granted Apr 15, 2003·23 cites·14 claims
- 0649US2010129432A1Microorganism-killing combinationUNIV TAIPEI MEDICAL·Filed 2008·Application pending·0 cites
- 0747US7139924B2IDE control device suitable for supplying a plurality of requested clock signals to various hard discsVIA TECH INC·Filed 2002·Granted Nov 21, 2006·1 cites·8 claims
- 0844US2003070018A1Delayed transaction method and device used in a PCI systemFiled 2002·Application pending·0 cites
- 0938US6694400B1PCI system controller capable of delayed transactionVIA TECH INC·Filed 1999·Granted Feb 17, 2004·11 cites·56 claims
- 1033US6753796B2Conversion circuit for burst signals referencing to various clocks and method for the sameVIA TECH INC·Filed 2003·Granted Jun 22, 2004·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →