Inventor · disambiguated record
Tse E. Wong
Also filed as: WONG TSE E · WONG TSE ERIC
10 granted patents·3 pending applications·103 citations·filing 1997–2018
88Inventor score
Top patents by PatentIndex Score
13 records- 0194US10446466B1Mechanically improved microelectronic thermal interface structure for low die stressRAYTHEON CO·Filed 2018·Granted Oct 15, 2019·15 cites·20 claims
- 0290US8921992B2Stacked wafer with coolant channelsRAYTHEON CO·Filed 2013·Granted Dec 30, 2014·13 cites·9 claims
- 0382US9648729B1Stress reduction interposer for ceramic no-lead surface mount electronic deviceRAYTHEON CO·Filed 2015·Granted May 9, 2017·6 cites·20 claims
- 0481US7605477B2Stacked integrated circuit assemblyRAYTHEON CO·Filed 2007·Granted Oct 20, 2009·11 cites·16 claims
- 0577US5899753ASpring-loaded ball contact connectorRAYTHEON CO·Filed 1997·Granted May 4, 1999·41 cites·12 claims
- 0673US9334154B2Hermetically sealed package having stress reducing layerRAYTHEON CO·Filed 2014·Granted May 10, 2016·2 cites·22 claims
- 0768US7888176B2Stacked integrated circuit assemblyRAYTHEON CO·Filed 2009·Granted Feb 15, 2011·4 cites·18 claims
- 0861US7298235B2Circuit board assembly and method of attaching a chip to a circuit board with a fillet bond not covering RF tracesRAYTHEON CO·Filed 2004·Granted Nov 20, 2007·11 cites·18 claims
- 0952US9708181B2Hermetically sealed package having stress reducing layerRAYTHEON CO·Filed 2016·Granted Jul 18, 2017·0 cites·4 claims
- 1043US2015380343A1Flip chip mmic having mounting stiffenerRAYTHEON CO·Filed 2014·Application pending·0 cites
- 1133US2018122777A1Hybrid micro-circuit device with stacked chip componentsRAYTHEON CO·Filed 2016·Application pending·0 cites
- 1232US9706662B2Adaptive interposer and electronic apparatusRAYTHEON CO·Filed 2015·Granted Jul 11, 2017·0 cites·20 claims
- 1331US2012155029A1Adaptive thermal gap padWONG TSE ERIC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →