Inventor · disambiguated record
Tushar R. Gheewala
Also filed as: GHEEWALA TUSHAR · GHEEWALA TUSHAR R
31 granted patents·1 pending application·2,012 citations·filing 1979–2007
98Inventor score
Files withCROSSCHECK TECHNOLOGY INC7IBM6VIRAGE LOGIC CORP6IN CHIP SYSTEMS INC4CROSS CHECK TECHNOLOGY INC2
Top patents by PatentIndex Score
32 records- 0197US6617621B1Gate array architecture using elevated metal levels for customizationVIRAGE LOGIC CORP·Filed 2000·Granted Sep 9, 2003·229 cites·53 claims
- 0297US6445065B1Routing driven, metal programmable integrated circuit architecture with multiple types of core cellsIN CHIP SYSTEMS INC·Filed 2000·Granted Sep 3, 2002·211 cites·25 claims
- 0397US5923059AIntegrated circuit cell architecture and routing schemeIN CHIP SYSTEMS INC·Filed 1996·Granted Jul 13, 1999·257 cites·42 claims
- 0496US5898194AIntegrated circuit cell architecture and routing schemeINCHIP SYSTEMS INC·Filed 1997·Granted Apr 27, 1999·282 cites·4 claims
- 0596US4365317ASuperconductive latch circuitIBM·Filed 1980·Granted Dec 21, 1982·73 cites·23 claims
- 0694US5923060AReduced area gate array cell design based on shifted placement of alternate rows of cellsIN CHIP SYSTEMS INC·Filed 1997·Granted Jul 13, 1999·148 cites·18 claims
- 0790US4749947AGrid-based, "cross-check" test structure for testing integrated circuitsCROSS CHECK SYSTEMS INC·Filed 1986·Granted Jun 7, 1988·84 cites·14 claims
- 0889US7069522B1Various methods and apparatuses to preserve a logic state for a volatile latch circuitVIRAGE LOGIC CORP·Filed 2004·Granted Jun 27, 2006·46 cites·27 claims
- 0989US6991947B1Hybrid semiconductor circuit with programmable intraconnectivityGHEEWALA TUSHAR·Filed 2004·Granted Jan 31, 2006·63 cites·14 claims
- 1088US7129562B1Dual-height cell with variable width power rail architectureVIRAGE LOGIC CORP·Filed 2004·Granted Oct 31, 2006·43 cites·6 claims
- 1188US6838713B1Dual-height cell with variable width power rail architectureVIRAGE LOGIC CORP·Filed 1999·Granted Jan 4, 2005·68 cites·22 claims
- 1285US7603634B2Various methods and apparatuses to preserve a logic state for a volatile latch circuitVIRAGE LOGIC CORP·Filed 2006·Granted Oct 13, 2009·15 cites·19 claims
- 1384US7219324B1Various methods and apparatuses to route multiple power rails to a cellVIRAGE LOGIC CORP·Filed 2004·Granted May 15, 2007·35 cites·21 claims
- 1484US4937826AMethod and apparatus for sensing defects in integrated circuit elementsCROSSCHECK TECHNOLOGY INC·Filed 1988·Granted Jun 26, 1990·44 cites·14 claims
- 1583US5065090AMethod for testing integrated circuits having a grid-based, "cross-check" teCROSS CHECK TECHNOLOGY INC·Filed 1988·Granted Nov 12, 1991·43 cites·3 claims
- 1682US6091090APower and signal routing technique for gate array designIN CHIP SYSTEMS INC·Filed 1997·Granted Jul 18, 2000·53 cites·20 claims
- 1782US5495486AMethod and apparatus for testing integrated circuitsCROSSCHECK TECHNOLOGY INC·Filed 1992·Granted Feb 27, 1996·48 cites·21 claims
- 1877US4691277ASmall instruction cache using branch target table to effect instruction prefetchIBM·Filed 1984·Granted Sep 1, 1987·53 cites·5 claims
- 1976US4313066ADirect coupled nonlinear injection Josephson logic circuitsIBM·Filed 1979·Granted Jan 26, 1982·15 cites·12 claims
- 2073US4845542AInterconnect for layered integrated circuit assemblyUNISYS CORP·Filed 1989·Granted Jul 4, 1989·41 cites·11 claims
- 2169US4533840ASoliton samplerIBM·Filed 1982·Granted Aug 6, 1985·19 cites·3 claims
- 2265US5157627AMethod and apparatus for setting desired signal level on storage elementCROSSCHECK TECHNOLOGY INC·Filed 1990·Granted Oct 20, 1992·26 cites·24 claims
- 2362US8132142B2Various methods and apparatuses to route multiple power rails to a cellSHERLEKAR DEEPAK D·Filed 2007·Granted Mar 6, 2012·2 cites·20 claims
- 2460US5471152AStorage element for delay testingCROSSCHECK TECHNOLOGY INC·Filed 1993·Granted Nov 28, 1995·25 cites·6 claims
- 2557US5202624AInterface between ic operational circuitry for coupling test signal from internal test matrixCROSS CHECK TECHNOLOGY INC·Filed 1991·Granted Apr 13, 1993·25 cites·8 claims
- 2653US5799021AMethod for direct access test of embedded cells and customization logicDUET TECHNOLOGIES INC·Filed 1997·Granted Aug 25, 1998·21 cites·10 claims
- 2750US5206862AMethod and apparatus for locally deriving test signals from previous response signalsCROSSCHECK TECHNOLOGY INC·Filed 1991·Granted Apr 27, 1993·15 cites·7 claims
- 2849US2005263959A1Board game method and apparatusGHEEWALA TUSHAR·Filed 2004·Application pending·0 cites
- 2944US5230001AMethod for testing a sequential circuit by splicing test vectors into sequential test patternCROSSCHECK TECHNOLOGY INC·Filed 1991·Granted Jul 20, 1993·12 cites·5 claims
- 3041US4392148AMoat-guarded Josephson devicesIBM·Filed 1980·Granted Jul 5, 1983·8 cites·17 claims
- 3139US4459495AJosephson current regulatorIBM·Filed 1981·Granted Jul 10, 1984·6 cites·1 claims
- 3229US5436801AMethod and structure for routing power for optimum cell utilization with two and three level metal in a partially predesigned integrated circuitCROSSCHECK TECHNOLOGY INC·Filed 1993·Granted Jul 25, 1995·2 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →