Inventor · disambiguated record
Tuhin Mahmud
Also filed as: MAHMUD TUHIN
10 granted patents·4 pending applications·71 citations·filing 2006–2023
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0192US11775720B2Integrated circuit development using machine learning-based prediction of power, performance, and areaIBM·Filed 2021·Granted Oct 3, 2023·3 cites·20 claims
- 0287US8365120B2Resolving global coupling timing and slew violations for buffer-dominated designsIBM·Filed 2010·Granted Jan 29, 2013·11 cites·21 claims
- 0386US8881089B1Physical synthesis optimization with fast metric checkIBM·Filed 2013·Granted Nov 4, 2014·11 cites·14 claims
- 0483US9092591B2Automatic generation of wire tag lists for a metal stackIBM·Filed 2014·Granted Jul 28, 2015·6 cites·19 claims
- 0582US8769468B1Automatic generation of wire tag lists for a metal stackIBM·Filed 2013·Granted Jul 1, 2014·6 cites·23 claims
- 0682US7484199B2Buffer insertion to reduce wirelength in VLSI circuitsIBM·Filed 2006·Granted Jan 27, 2009·9 cites·14 claims
- 0779US7448007B2Slew constrained minimum cost bufferingIBM·Filed 2006·Granted Nov 4, 2008·9 cites·4 claims
- 0877US7895557B2Concurrent buffering and layer assignment in integrated circuit layoutIBM·Filed 2008·Granted Feb 22, 2011·10 cites·2 claims
- 0971US11205092B2Clustering simulation failures for triage and debuggingIBM·Filed 2019·Granted Dec 21, 2021·2 cites·18 claims
- 1068US7890905B2Slew constrained minimum cost bufferingIBM·Filed 2008·Granted Feb 15, 2011·4 cites·8 claims
- 1154US2009064080A1Buffer insertion to reduce wirelength in vlsi circuitsALPERT CHARLES J·Filed 2008·Application pending·0 cites
- 1253US2009013299A1Buffer insertion to reduce wirelength in vlsi circuitsALPERT CHARLES J·Filed 2008·Application pending·0 cites
- 1351US2025036850A1Method of predicting failure in a circuit design caused by noise impactIBM·Filed 2023·Application pending·0 cites
- 1442US2007283301A1System and Method of Eliminating Electrical ViolationsKARANDIKAR ARVIND K·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →