Inventor · disambiguated record
Tz-Jun Kuo
Also filed as: KUO TZ-JUN
15 granted patents·3 pending applications·109 citations·filing 2012–2025
91Inventor score
Top patents by PatentIndex Score
18 records- 0198US9972529B2Method of forming metal interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 15, 2018·35 cites·20 claims
- 0298US9613856B1Method of forming metal interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Apr 4, 2017·38 cites·20 claims
- 0395US10163786B2Method of forming metal interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 25, 2018·11 cites·20 claims
- 0491US9343356B2Back end of the line (BEOL) interconnect schemeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted May 17, 2016·14 cites·19 claims
- 0583US9640431B2Method for via plating with seed layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 2, 2017·2 cites·20 claims
- 0682US9054163B2Method for via plating with seed layerTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jun 9, 2015·3 cites·20 claims
- 0781US2025279315A1Interconnect structure without barrier layer on bottom surface of viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0880US8749060B2Method of semiconductor integrated circuit fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Jun 10, 2014·4 cites·20 claims
- 0975US12308282B2Interconnect structure without barrier layer on bottom surface of viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted May 20, 2025·0 cites·20 claims
- 1072US11715689B2Method of forming metal interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 1, 2023·0 cites·20 claims
- 1172US10453740B2Interconnect structure without barrier layer on bottom surface of viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Oct 22, 2019·1 cites·20 claims
- 1271US9324608B2Method for via plating with seed layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Apr 26, 2016·1 cites·20 claims
- 1365US2022352012A1Via structure and methods for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Application pending·0 cites
- 1464US11551967B2Via structure and methods for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jan 10, 2023·0 cites·20 claims
- 1562US11322391B2Interconnect structure without barrier layer on bottom surface of viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted May 3, 2022·0 cites·20 claims
- 1662US10714424B2Method of forming metal interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jul 14, 2020·0 cites·20 claims
- 1757US2017236750A1Method for Via Plating with Seed LayerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Application pending·0 cites
- 1855US9842767B2Method of forming an interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 12, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →