Inventor · disambiguated record
Ulrike Gruening
Also filed as: GRUENING ULRIKE
57 granted patents·2 pending applications·1,823 citations·filing 1997–2004
99Inventor score
Top patents by PatentIndex Score
59 records- 0196US6339241B1Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitchIBM·Filed 2000·Granted Jan 15, 2002·73 cites·15 claims
- 0295US6630379B2Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitchIBM·Filed 2001·Granted Oct 7, 2003·62 cites·20 claims
- 0394US6573137B1Single sided buried strapINFINEON TECHNOLOGIES CORP·Filed 2000·Granted Jun 3, 2003·58 cites·12 claims
- 0494US6429068B1Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnectIBM·Filed 2001·Granted Aug 6, 2002·62 cites·20 claims
- 0594US6177698B1Formation of controlled trench top isolation layers for vertical transistorsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Jan 23, 2001·144 cites·10 claims
- 0692US6437381B1Semiconductor memory device with reduced orientation-dependent oxidation in trench structuresIBM·Filed 2000·Granted Aug 20, 2002·52 cites·13 claims
- 0792US6258659B1Embedded vertical DRAM cells and dual workfunction logic gatesIBM·Filed 2000·Granted Jul 10, 2001·56 cites·6 claims
- 0891US6437388B1Compact trench capacitor memory cell with body contactINFINEON TECHNOLOGIES AG·Filed 2001·Granted Aug 20, 2002·58 cites·14 claims
- 0991US6348374B1Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structureIBM·Filed 2000·Granted Feb 19, 2002·45 cites·11 claims
- 1089US6255683B1Dynamic random access memoryINFINEON TECHNOLOGIES AG·Filed 1998·Granted Jul 3, 2001·66 cites·2 claims
- 1188US6593612B2Structure and method for forming a body contact for vertical transistor cellsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 15, 2003·37 cites·4 claims
- 1287US6593613B1Memory cell for plateline sensingINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 15, 2003·40 cites·29 claims
- 1387US6074909AApparatus and method for forming controlled deep trench top isolation layersSIEMENS AG·Filed 1998·Granted Jun 13, 2000·71 cites·25 claims
- 1485US6727539B2Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnectIBM·Filed 2002·Granted Apr 27, 2004·26 cites·11 claims
- 1585US6555862B1Self-aligned buried strap for vertical transistorsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Apr 29, 2003·29 cites·10 claims
- 1685US6362040B1Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substratesINFINEON TECHNOLOGIES AG·Filed 2000·Granted Mar 26, 2002·41 cites·31 claims
- 1785US6319788B1Semiconductor structure and manufacturing methodsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Nov 20, 2001·58 cites·7 claims
- 1885US6265742B1Memory cell structure and fabricationSIEMENS AG·Filed 1999·Granted Jul 24, 2001·51 cites·12 claims
- 1983US6194755B1Low-resistance salicide fill for trench capacitorsIBM·Filed 1998·Granted Feb 27, 2001·47 cites·21 claims
- 2082US6153902AVertical DRAM cell with wordline self-aligned to storage trenchIBM·Filed 1999·Granted Nov 28, 2000·37 cites·15 claims
- 2181US6812091B1Trench capacitor memory cellINFINEON TECHNOLOGIES AG·Filed 2000·Granted Nov 2, 2004·23 cites·13 claims
- 2280US6426251B2Process for manufacturing a crystal axis-aligned vertical side wall deviceIBM·Filed 2001·Granted Jul 30, 2002·17 cites·11 claims
- 2380US6320215B1Crystal-axis-aligned vertical side wall deviceIBM·Filed 1999·Granted Nov 20, 2001·31 cites·4 claims
- 2479US6291335B1Locally folded split level bitline wiringINFINEON TECHNOLOGIES AG·Filed 1999·Granted Sep 18, 2001·47 cites·22 claims
- 2578US6331459B1Use of dummy poly spacers and divot fill techniques for DT-aligned processing after STI formation for advanced deep trench capacitor DRAMINFINEON TECHNOLOGIES AG·Filed 1999·Granted Dec 18, 2001·42 cites·36 claims
- 2678US6093614AMemory cell structure and fabricationSIEMENS AG·Filed 1998·Granted Jul 25, 2000·38 cites·7 claims
- 2776US6399978B2Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation regionIBM·Filed 2000·Granted Jun 4, 2002·19 cites·8 claims
- 2876US6190971B1Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation regionIBM·Filed 1999·Granted Feb 20, 2001·41 cites·14 claims
- 2974US6376324B1Collar process for reduced deep trench edge biasIBM·Filed 2000·Granted Apr 23, 2002·15 cites·16 claims
- 3073US6486024B1Integrated circuit trench device with a dielectric collar stack, and method of forming thereofINFINEON TECHNOLOGIES AG·Filed 2000·Granted Nov 26, 2002·14 cites·20 claims
- 3173US6204140B1Dynamic random access memoryINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Mar 20, 2001·33 cites·7 claims
- 3271US6348388B1Process for fabricating a uniform gate oxide of a vertical transistorIBM·Filed 2000·Granted Feb 19, 2002·12 cites·11 claims
- 3371US6323103B1Method for fabricating transistorsSIEMENS AG·Filed 1998·Granted Nov 27, 2001·39 cites·41 claims
- 3470US6605860B1Semiconductor structures and manufacturing methodsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 12, 2003·10 cites·2 claims
- 3570US6188598B1Reducing impact of coupling noiseINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Feb 13, 2001·28 cites·26 claims
- 3670US6184091B1Formation of controlled trench top isolation layers for vertical transistorsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Feb 6, 2001·32 cites·19 claims
- 3769US6544850B1Dynamic random access memoryINFINEON TECHNOLOGIES AG·Filed 2000·Granted Apr 8, 2003·14 cites·24 claims
- 3869US6184107B1Capacitor trench-top dielectric for self-aligned device isolationIBM·Filed 1999·Granted Feb 6, 2001·37 cites·7 claims
- 3966US6762447B1Field-shield-trench isolation for gigabit DRAMsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Jul 13, 2004·33 cites·15 claims
- 4066US6372567B1Control of oxide thickness in vertical transistor structuresINFINEON TECHNOLOGIES AG·Filed 2000·Granted Apr 16, 2002·10 cites·9 claims
- 4166US6013937ABuffer layer for improving control of layer thicknessSIEMENS AG·Filed 1997·Granted Jan 11, 2000·32 cites·5 claims
- 4262US6150670AProcess for fabricating a uniform gate oxide of a vertical transistorIBM·Filed 1999·Granted Nov 21, 2000·22 cites·9 claims
- 4361US6369419B1Self-aligned near surface strap for high density trench DRAMSIBM·Filed 2000·Granted Apr 9, 2002·6 cites·20 claims
- 4461US6359299B1Apparatus and method for forming controlled deep trench top isolation layersINFINEON TECHNOLOGIES AG·Filed 2000·Granted Mar 19, 2002·6 cites·8 claims
- 4560US6429092B1Collar formation by selective oxide depositionINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 6, 2002·7 cites·15 claims
- 4657US6740555B1Semiconductor structures and manufacturing methodsINFINEON TECHNOLOGIES AG·Filed 1999·Granted May 25, 2004·16 cites·7 claims
- 4755US6271142B1Process for manufacture of trench DRAM capacitor buried platesINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Aug 7, 2001·19 cites·19 claims
- 4854US6967133B2Method for fabricating a semiconductor structureINFINEON TECHNOLOGIES AG·Filed 2003·Granted Nov 22, 2005·4 cites·15 claims
- 4954US6759291B2Self-aligned near surface strap for high density trench DRAMSIBM·Filed 2002·Granted Jul 6, 2004·4 cites·20 claims
- 5051US6451648B1Process for buried-strap self-aligned to deep storage trenchIBM·Filed 1999·Granted Sep 17, 2002·12 cites·22 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Ulrike Gruening files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →