Inventor · disambiguated record
Unsoon Kim
Also filed as: KIM UNSOON
53 granted patents·7 pending applications·663 citations·filing 1997–2024
98Inventor score
Files withADVANCED MICRO DEVICES INC20CYPRESS SEMICONDUCTOR CORP19SPANSION LLC14LEE CHUNGHO2WU YIDER2
Top patents by PatentIndex Score
60 records- 0196US9853039B1Split-gate flash cell formed on recessed substrateCYPRESS SEMICONDUCTOR CORP·Filed 2017·Granted Dec 26, 2017·16 cites·19 claims
- 0295US12029041B2Method of forming high-voltage transistor with thin gate polyCYPRESS SEMICONDUCTOR CORP·Filed 2023·Granted Jul 2, 2024·1 cites·20 claims
- 0395US6004862ACore array and periphery isolation techniqueADVANCED MICRO DEVICES INC·Filed 1998·Granted Dec 21, 1999·219 cites·8 claims
- 0494US6509232B1Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory deviceADVANCED MICRO DEVICES INC·Filed 2001·Granted Jan 21, 2003·65 cites·20 claims
- 0590US10014380B2Memory first process flow and deviceCYPRESS SEMICONDUCTOR CORP·Filed 2016·Granted Jul 3, 2018·4 cites·14 claims
- 0689US9368606B2Memory first process flow and deviceSPANSION LLC·Filed 2012·Granted Jun 14, 2016·9 cites·24 claims
- 0788US10872898B2Embedded non-volatile memory device and fabrication method of the sameCYPRESS SEMICONDUCTOR CORP·Filed 2017·Granted Dec 22, 2020·4 cites·25 claims
- 0887US6664191B1Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly spaceADVANCED MICRO DEVICES INC·Filed 2001·Granted Dec 16, 2003·38 cites·29 claims
- 0983US9917166B2Memory first process flow and deviceCYPRESS SEMICONDUCTOR CORP·Filed 2016·Granted Mar 13, 2018·3 cites·14 claims
- 1081US9209197B2Memory gate landing pad made from dummy featuresSPANSION LLC·Filed 2012·Granted Dec 8, 2015·5 cites·15 claims
- 1180US7985687B1System and method for improving reliability in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2005·Granted Jul 26, 2011·7 cites·18 claims
- 1280US7842618B2System and method for improving mesa width in a semiconductor deviceSPANSION LLC·Filed 2005·Granted Nov 30, 2010·5 cites·17 claims
- 1379US5907781AProcess for fabricating an integrated circuit with a self-aligned contactADVANCED MICRO DEVICES INC·Filed 1998·Granted May 25, 1999·59 cites·20 claims
- 1477US10242996B2Method of forming high-voltage transistor with thin gate polyCYPRESS SEMICONDUCTOR CORP·Filed 2017·Granted Mar 26, 2019·1 cites·20 claims
- 1576US8802537B1System and method for improving reliability in a semiconductor deviceWU YIDER·Filed 2005·Granted Aug 12, 2014·6 cites·12 claims
- 1676US6693009B1Flash memory cell with minimized floating gate to drain/source overlap for minimizing charge leakageADVANCED MICRO DEVICES INC·Filed 2000·Granted Feb 17, 2004·25 cites·20 claims
- 1774US11690227B2Method of forming high-voltage transistor with thin gate polyCYPRESS SEMICONDUCTOR CORP·Filed 2021·Granted Jun 27, 2023·0 cites·21 claims
- 1874US6607925B1Hard mask removal process including isolation dielectric refillADVANCED MICRO DEVICES INC·Filed 2002·Granted Aug 19, 2003·16 cites·12 claims
- 1973US11342429B2Memory first process flow and deviceCYPRESS SEMICONDUCTOR CORP·Filed 2020·Granted May 24, 2022·0 cites·18 claims
- 2073US6433383B1Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 1999·Granted Aug 13, 2002·50 cites·4 claims
- 2172US7307002B2Non-critical complementary masking method for poly-1 definition in flash memory device fabricationSPANSION LLC·Filed 2005·Granted Dec 11, 2007·4 cites·10 claims
- 2270US10141393B1Three dimensional capacitorCYPRESS SEMICONDUCTOR CORP·Filed 2016·Granted Nov 27, 2018·1 cites·17 claims
- 2368US7767517B2Semiconductor memory comprising dual charge storage nodes and methods for its fabricationSPANSION LLC·Filed 2006·Granted Aug 3, 2010·3 cites·17 claims
- 2468US6924220B1Self-aligned gate formation using polysilicon polish with peripheral protective layerADVANCED MICRO DEVICES INC·Filed 2001·Granted Aug 2, 2005·12 cites·13 claims
- 2568US6610577B1Self-aligned polysilicon polishADVANCED MICRO DEVICES INC·Filed 2002·Granted Aug 26, 2003·11 cites·13 claims
- 2666US10818761B2Memory first process flow and deviceCYPRESS SEMICONDUCTOR CORP·Filed 2019·Granted Oct 27, 2020·0 cites·8 claims
- 2766US7679129B1System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor deviceSPANSION LLC·Filed 2005·Granted Mar 16, 2010·3 cites·9 claims
- 2863US10403731B2Memory first process flow and deviceCYPRESS SEMICONDUCTOR CORP·Filed 2018·Granted Sep 3, 2019·0 cites·20 claims
- 2963US6040597AIsolation boundaries in flash memory coresADVANCED MICRO DEVICES INC·Filed 1998·Granted Mar 21, 2000·29 cites·11 claims
- 3062US6764920B1Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devicesADVANCED MICRO DEVICES INC·Filed 2002·Granted Jul 20, 2004·10 cites·22 claims
- 3162US2019304990A1Method of Forming High-Voltage Transistor with Thin Gate PolyCYPRESS SEMICONDUCTOR CORP·Filed 2019·Application pending·0 cites
- 3261US2024206183A1High-voltage transistor with thin high-k metal gate and method of fabrication thereofCYPRESS SEMICONDUCTOR CORP·Filed 2024·Application pending·0 cites
- 3360US6548855B1Non-volatile memory dielectric as charge pump dielectricADVANCED MICRO DEVICES INC·Filed 2002·Granted Apr 15, 2003·7 cites·6 claims
- 3459US2021134811A1Embedded non-volatile memory device and fabrication method of the sameCYPRESS SEMICONDUCTOR CORP·Filed 2020·Application pending·0 cites
- 3557US6566230B1Shallow trench isolation spacer for weff improvementADVANCED MICRO DEVICES INC·Filed 2001·Granted May 20, 2003·7 cites·10 claims
- 3656US10923601B2Charge trapping split gate device and method of fabricating sameCYPRESS SEMICONDUCTOR CORP·Filed 2018·Granted Feb 16, 2021·0 cites·20 claims
- 3756US10497710B2Split-gate flash cell formed on recessed substrateCYPRESS SEMICONDUCTOR CORP·Filed 2017·Granted Dec 3, 2019·0 cites·21 claims
- 3855US10177040B2Manufacturing of FET devices having lightly doped drain and source regionsCYPRESS SEMICONDUCTOR CORP·Filed 2017·Granted Jan 8, 2019·0 cites·18 claims
- 3955US8598645B2System and method for improving mesa width in a semiconductor deviceKIM UNSOON·Filed 2010·Granted Dec 3, 2013·1 cites·20 claims
- 4054US9917211B2Flash memory cells having trenched storage elementsSPANSION LLC·Filed 2014·Granted Mar 13, 2018·0 cites·8 claims
- 4152US5981341ASidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory coreADVANCED MICRO DEVICES INC·Filed 1997·Granted Nov 9, 1999·18 cites·11 claims
- 4251US7439141B2Shallow trench isolation approach for improved STI corner roundingSPANSION LLC·Filed 2002·Granted Oct 21, 2008·4 cites·8 claims
- 4351US7078314B1Memory device having improved periphery and core isolationADVANCED MICRO DEVICES INC·Filed 2003·Granted Jul 18, 2006·4 cites·11 claims
- 4451US2014167141A1Charge Trapping Split Gate Embedded Flash Memory and Associated MethodsSPANSION LLC·Filed 2012·Application pending·0 cites
- 4550US9966477B2Charge trapping split gate device and method of fabricating sameCYPRESS SEMICONDUCTOR CORP·Filed 2012·Granted May 8, 2018·0 cites·19 claims
- 4650US9922833B2Charge trapping split gate embedded flash memory and associated methodsCYPRESS SEMICONDUCTOR CORP·Filed 2015·Granted Mar 20, 2018·0 cites·18 claims
- 4748US8742486B2Flash memory cells having trenched storage elementsZHENG WEI·Filed 2007·Granted Jun 3, 2014·0 cites·16 claims
- 4848US2014210012A1Manufacturing of FET Devices Having Lightly Doped Drain and Source RegionsSPANSION LLC·Filed 2013·Application pending·0 cites
- 4948US2014167220A1Three dimensional capacitorSPANSION LLC·Filed 2012·Application pending·0 cites
- 5045US8076712B2Semiconductor memory comprising dual charge storage nodes and methods for its fabricationLEE CHUNGHO·Filed 2010·Granted Dec 13, 2011·0 cites·6 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →