Inventor · disambiguated record
Vamsee Vardhan Chivukula
Also filed as: CHIVUKULA VAMSEE VARDHAN
10 granted patents·2 pending applications·14 citations·filing 2017–2025
83Inventor score
Files withINTEL CORP12
Top patents by PatentIndex Score
12 records- 0192US10861126B1Asynchronous execution mechanismINTEL CORP·Filed 2019·Granted Dec 8, 2020·5 cites·20 claims
- 0286US10424107B2Hierarchical depth buffer back annotatonINTEL CORP·Filed 2017·Granted Sep 24, 2019·5 cites·22 claims
- 0386US10102609B1Low granularity coarse depth test efficiency enhancementINTEL CORP·Filed 2017·Granted Oct 16, 2018·4 cites·30 claims
- 0473US2025259371A1Dynamic routing of texture loads in graphics processingINTEL CORP·Filed 2025·Application pending·0 cites
- 0570US11615584B2Hierarchical depth buffer back annotationINTEL CORP·Filed 2021·Granted Mar 28, 2023·0 cites·20 claims
- 0668US12288284B2Dynamic routing of texture loads in graphics processingINTEL CORP·Filed 2021·Granted Apr 29, 2025·0 cites·20 claims
- 0767US11494867B2Asynchronous execution mechanismINTEL CORP·Filed 2020·Granted Nov 8, 2022·0 cites·20 claims
- 0867US11250539B2Low granularity coarse depth test efficiency enhancementINTEL CORP·Filed 2020·Granted Feb 15, 2022·0 cites·20 claims
- 0960US11080925B2Hierarchical depth buffer back annotationINTEL CORP·Filed 2019·Granted Aug 3, 2021·0 cites·20 claims
- 1056US10748242B2Low granularity coarse depth test efficiency enhancementINTEL CORP·Filed 2018·Granted Aug 18, 2020·0 cites·20 claims
- 1143US2022383569A1Small polygon rasterizationINTEL CORP·Filed 2021·Application pending·0 cites
- 1242US10319138B2Graphics with early stencil testINTEL CORP·Filed 2017·Granted Jun 11, 2019·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →