Inventor · disambiguated record
Vaishnav Srinivas
Also filed as: SRINIVAS VAISHNAV
36 granted patents·5 pending applications·276 citations·filing 2002–2025
97Inventor score
Top patents by PatentIndex Score
41 records- 0196US7075175B2Systems and methods for testing packaged diesQUALCOMM INC·Filed 2004·Granted Jul 11, 2006·127 cites·23 claims
- 0293US10169262B2Low-power clocking for a high-speed memory interfaceQUALCOMM INC·Filed 2016·Granted Jan 1, 2019·13 cites·30 claims
- 0391US9910482B2Memory interface with adjustable voltage and termination and methods of useQUALCOMM INC·Filed 2015·Granted Mar 6, 2018·9 cites·14 claims
- 0488US11120863B2System and method for compensating for SDRAM signal timing drift through periodic write trainingQUALCOMM INC·Filed 2020·Granted Sep 14, 2021·3 cites·30 claims
- 0587US9734878B1Systems and methods for individually configuring dynamic random access memories sharing a common command access busQUALCOMM INC·Filed 2016·Granted Aug 15, 2017·5 cites·30 claims
- 0685US8008944B2Low voltage differential signaling driver with programmable on-chip resistor terminationQUALCOMM INC·Filed 2008·Granted Aug 30, 2011·13 cites·22 claims
- 0784US9088445B2Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speedQUALCOMM INC·Filed 2013·Granted Jul 21, 2015·7 cites·27 claims
- 0882US8593203B2High signal level compliant input/output circuitsSHANKAR VIJAY·Filed 2008·Granted Nov 26, 2013·13 cites·19 claims
- 0982US7768299B2Voltage tolerant floating N-well circuitQUALCOMM INC·Filed 2007·Granted Aug 3, 2010·12 cites·21 claims
- 1081US11662765B1System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfacesQUALCOMM INC·Filed 2022·Granted May 30, 2023·1 cites·30 claims
- 1181US9881656B2Dynamic random access memory (DRAM) backchannel communication systems and methodsQUALCOMM INC·Filed 2015·Granted Jan 30, 2018·5 cites·18 claims
- 1281US9312326B2Metal-insulator-metal capacitor structuresQUALCOMM INC·Filed 2015·Granted Apr 12, 2016·4 cites·9 claims
- 1381US7605618B2Digital output driver and input buffer using thin-oxide field effect transistorsQUALCOMM INC·Filed 2006·Granted Oct 20, 2009·11 cites·29 claims
- 1479US10613613B2Memory interface with adjustable voltage and termination and methods of useQUALCOMM INC·Filed 2018·Granted Apr 7, 2020·2 cites·20 claims
- 1577US9041148B2Metal-insulator-metal capacitor structuresQUALCOMM INC·Filed 2013·Granted May 26, 2015·4 cites·10 claims
- 1673US7772887B2High signal level compliant input/output circuitsQUALCOMM INC·Filed 2008·Granted Aug 10, 2010·6 cites·17 claims
- 1772US9032358B2Integrated circuit floorplan for compact clock distributionQUALCOMM INC·Filed 2013·Granted May 12, 2015·3 cites·26 claims
- 1872US7804334B2High signal level compliant input/output circuitsQUALCOMM INC·Filed 2008·Granted Sep 28, 2010·6 cites·14 claims
- 1969US9633698B2Dynamic control of signaling power based on an error rateQUALCOMM INC·Filed 2014·Granted Apr 25, 2017·2 cites·30 claims
- 2069US9438208B2Wide-band duty cycle correction circuitQUALCOMM INC·Filed 2014·Granted Sep 6, 2016·3 cites·21 claims
- 2164US9397646B2Delay circuitQUALCOMM INC·Filed 2014·Granted Jul 19, 2016·3 cites·28 claims
- 2262US7772831B2Systems and methods for testing packaged diesQUALCOMM INC·Filed 2006·Granted Aug 10, 2010·3 cites·20 claims
- 2361US2025342135A1Apparatus and methods for multi-memory configuration support within die architectures and packagingQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2460US8106699B2High signal level compliant input/output circuitsSHANKAR VIJAY·Filed 2008·Granted Jan 31, 2012·4 cites·21 claims
- 2559US9246716B2Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speedQUALCOMM INC·Filed 2015·Granted Jan 26, 2016·1 cites·28 claims
- 2658US9871012B2Method and apparatus for routing die signals using external interconnectsQUALCOMM INC·Filed 2013·Granted Jan 16, 2018·1 cites·31 claims
- 2758US9734890B1Systems and methods for individually configuring dynamic random access memories sharing a common command access busQUALCOMM INC·Filed 2016·Granted Aug 15, 2017·1 cites·30 claims
- 2858US7302020B2Encoded multi-access bus system and methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Nov 27, 2007·3 cites·37 claims
- 2957US9767868B2Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatusesQUALCOMM INC·Filed 2015·Granted Sep 19, 2017·1 cites·19 claims
- 3056US7843234B2Break-before-make predriver and level-shifterQUALCOMM INC·Filed 2004·Granted Nov 30, 2010·7 cites·21 claims
- 3155US11493949B2Clocking scheme to receive dataQUALCOMM INC·Filed 2020·Granted Nov 8, 2022·0 cites·20 claims
- 3255US2025349813A1Package-on-package with different types of memoryQUALCOMM INC·Filed 2025·Application pending·0 cites
- 3354US8363538B2Orthogonal data link, and associated methodsHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jan 29, 2013·2 cites·29 claims
- 3452US2024038672A1Package comprising integrated devicesQUALCOMM INC·Filed 2022·Application pending·0 cites
- 3548US10224081B2Dynamic random access memory (DRAM) backchannel communication systems and methodsQUALCOMM INC·Filed 2017·Granted Mar 5, 2019·0 cites·3 claims
- 3647US9947377B2Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatusesQUALCOMM INC·Filed 2017·Granted Apr 17, 2018·0 cites·19 claims
- 3747US8138814B2High signal level compliant input/output circuitsSHANKAR VIJAY·Filed 2008·Granted Mar 20, 2012·1 cites·18 claims
- 3842US2015294970A1Capacitor, resistor and resistor-capacitor componentsQUALCOMM INC·Filed 2014·Application pending·0 cites
- 3941US8957714B2Measure-based delay circuitQUALCOMM INC·Filed 2013·Granted Feb 17, 2015·0 cites·13 claims
- 4036US2015213850A1Serial data transmission for dynamic random access memory (dram) interfacesQUALCOMM INC·Filed 2015·Application pending·0 cites
- 4132US7656743B2Clock signal generation techniques for memories that do not generate a strobeQUALCOMM INC·Filed 2006·Granted Feb 2, 2010·0 cites·34 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →