Inventor · disambiguated record
Victor Roberts Augsburg
Also filed as: AUGSBURG VICTOR R · AUGSBURG VICTOR ROBERTS
25 granted patents·4 pending applications·419 citations·filing 1996–2009
96Inventor score
Top patents by PatentIndex Score
29 records- 0188US5996092ASystem and method for tracing program execution within a processor before and after a triggering eventIBM·Filed 1996·Granted Nov 30, 1999·127 cites·4 claims
- 0286US7587580B2Power efficient instruction prefetch mechanismQUALCOMM INC·Filed 2005·Granted Sep 8, 2009·14 cites·11 claims
- 0385US7366869B2Method and system for optimizing translation lookaside buffer entriesQUALCOMM INC·Filed 2005·Granted Apr 29, 2008·15 cites·14 claims
- 0483US6826747B1System and method for tracing program instructions before and after a trace triggering event within a processorIBM·Filed 1999·Granted Nov 30, 2004·88 cites·19 claims
- 0583US6826656B2Reducing power in a snooping cache based multiprocessor environmentIBM·Filed 2002·Granted Nov 30, 2004·35 cites·27 claims
- 0679US7426626B2TLB lock indicatorQUALCOMM INC·Filed 2005·Granted Sep 16, 2008·9 cites·18 claims
- 0775US7437537B2Methods and apparatus for predicting unaligned memory accessQUALCOMM INC·Filed 2005·Granted Oct 14, 2008·7 cites·18 claims
- 0873US6834378B2System on a chip bus with automatic pipeline stage insertion for timing closureIBM·Filed 2002·Granted Dec 21, 2004·15 cites·11 claims
- 0970US7035958B2Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the targetIBM·Filed 2002·Granted Apr 25, 2006·15 cites·21 claims
- 1069US7366877B2Speculative instruction issue in a simultaneously multithreaded processorIBM·Filed 2003·Granted Apr 29, 2008·12 cites·14 claims
- 1168US7330941B2Global modified indicator to reduce power consumption on cache missQUALCOMM INC·Filed 2005·Granted Feb 12, 2008·4 cites·10 claims
- 1267US7721067B2Translation lookaside buffer manipulationQUALCOMM INC·Filed 2006·Granted May 18, 2010·4 cites·22 claims
- 1366US7650466B2Method and apparatus for managing cache partitioning using a dynamic boundaryQUALCOMM INC·Filed 2005·Granted Jan 19, 2010·3 cites·24 claims
- 1466US6948053B2Efficiently calculating a branch target addressIBM·Filed 2002·Granted Sep 20, 2005·11 cites·41 claims
- 1565US6907502B2Method for moving snoop pushes to the front of a request queueIBM·Filed 2002·Granted Jun 14, 2005·10 cites·27 claims
- 1664US7725625B2Latency insensitive FIFO signaling protocolQUALCOMM INC·Filed 2008·Granted May 25, 2010·2 cites·20 claims
- 1763US8661229B2Power efficient instruction prefetch mechanismSARTORIUS THOMAS ANDREW·Filed 2009·Granted Feb 25, 2014·2 cites·20 claims
- 1863US6816962B2Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructionsIBM·Filed 2002·Granted Nov 9, 2004·9 cites·16 claims
- 1957US8239657B2Address translation method and apparatusKOPEC BRIAN JOSEPH·Filed 2007·Granted Aug 7, 2012·3 cites·26 claims
- 2057US6513134B1System and method for tracing program execution within a superscalar processorIBM·Filed 1999·Granted Jan 28, 2003·30 cites·26 claims
- 2153US8527713B2Cache locking without interference from normal allocationsAUGSBURG VICTOR ROBERTS·Filed 2006·Granted Sep 3, 2013·1 cites·21 claims
- 2253US7725684B2Speculative instruction issue in a simultaneously multithreaded processorIBM·Filed 2008·Granted May 25, 2010·0 cites·13 claims
- 2351US7296175B2System on a chip bus with automatic pipeline stage insertion for timing closureIBM·Filed 2004·Granted Nov 13, 2007·1 cites·9 claims
- 2448US7454538B2Latency insensitive FIFO signaling protocolQUALCOMM INC·Filed 2005·Granted Nov 18, 2008·0 cites·14 claims
- 2547US6807608B2Multiprocessor environment supporting variable-sized coherency transactionsIBM·Filed 2002·Granted Oct 19, 2004·2 cites·24 claims
- 2643US2007094476A1Updating multiple levels of translation lookaside buffers (TLBs) fieldAUGSBURG VICTOR R·Filed 2005·Application pending·0 cites
- 2742US2004226011A1Multi-threaded microprocessor with queue flushingIBM·Filed 2003·Application pending·0 cites
- 2839US2007005933A1Preventing multiple translation lookaside buffer accesses for a same page in memoryKOPEC BRIAN J·Filed 2005·Application pending·0 cites
- 2937US2006174066A1Fractional-word writable architected register for direct accumulation of misaligned dataBRIDGES JEFFREY T·Filed 2005·Application pending·0 cites
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