Inventor · disambiguated record
Victor Chan
Also filed as: CHAN VICTOR · CHAN VICTOR S · CHAN VICTOR W C
41 granted patents·10 pending applications·721 citations·filing 2003–2022
97Inventor score
Top patents by PatentIndex Score
51 records- 0199US6821826B1Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafersIBM·Filed 2003·Granted Nov 23, 2004·391 cites·19 claims
- 0295US7001844B2Material for contact etch layer to enhance device performanceIBM·Filed 2004·Granted Feb 21, 2006·74 cites·35 claims
- 0395US6939814B2Increasing carrier mobility in NFET and PFET transistors on a common waferIBM·Filed 2003·Granted Sep 6, 2005·97 cites·11 claims
- 0489US10943990B2Gate contact over active enabled by alternative spacer scheme and claw-shaped capIBM·Filed 2018·Granted Mar 9, 2021·5 cites·15 claims
- 0589US7309637B2Method to enhance device performance with selective stress reliefCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Dec 18, 2007·14 cites·26 claims
- 0687US7193254B2Structure and method of applying stresses to PFET and NFET transistor channels for improved performanceCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Mar 20, 2007·37 cites·9 claims
- 0786US9929250B1Semiconductor device including optimized gate stack profileIBM·Filed 2016·Granted Mar 27, 2018·5 cites·19 claims
- 0886US7473593B2Semiconductor transistors with expanded top portions of gatesIBM·Filed 2006·Granted Jan 6, 2009·9 cites·16 claims
- 0985US9355887B2Dual trench isolation for CMOS with hybrid orientationsCHAN VICTOR·Filed 2012·Granted May 31, 2016·6 cites·11 claims
- 1084US9837351B1Avoiding gate metal via shorting to source or drain contactsIBM·Filed 2016·Granted Dec 5, 2017·3 cites·16 claims
- 1182US10217839B2Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FETGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 26, 2019·3 cites·7 claims
- 1282US8338245B2Integrated circuit system employing stress-engineered spacersLEE JAE GON·Filed 2008·Granted Dec 25, 2012·10 cites·10 claims
- 1381US11222820B2Self-aligned gate cap including an etch-stop layerIBM·Filed 2018·Granted Jan 11, 2022·2 cites·9 claims
- 1481US9748358B2Gap fill of metal stack in replacement gate processIBM·Filed 2015·Granted Aug 29, 2017·3 cites·20 claims
- 1580US8753929B2Structure fabrication methodIBM·Filed 2013·Granted Jun 17, 2014·3 cites·14 claims
- 1678US7659174B2Method to enhance device performance with selective stress reliefCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Feb 9, 2010·6 cites·18 claims
- 1777US7442611B2Method of applying stresses to PFET and NFET transistor channels for improved performanceIBM·Filed 2007·Granted Oct 28, 2008·6 cites·7 claims
- 1876US8466503B2Semiconductor transistors with expanded top portions of gatesANDERSON BRENT ALAN·Filed 2008·Granted Jun 18, 2013·4 cites·7 claims
- 1974US10043744B2Avoiding gate metal via shorting to source or drain contactsIBM·Filed 2017·Granted Aug 7, 2018·1 cites·20 claims
- 2073US7816909B2Mechanical stress characterization in semiconductor deviceIBM·Filed 2008·Granted Oct 19, 2010·4 cites·10 claims
- 2172US7211869B2Increasing carrier mobility in NFET and PFET transistors on a common waferIBM·Filed 2005·Granted May 1, 2007·4 cites·9 claims
- 2271US7482216B2Substrate engineering for optimum CMOS device performanceIBM·Filed 2006·Granted Jan 27, 2009·4 cites·10 claims
- 2370US12150393B2Heater for phase change material memory cellIBM·Filed 2022·Granted Nov 19, 2024·0 cites·19 claims
- 2469US7148559B2Substrate engineering for optimum CMOS device performanceIBM·Filed 2003·Granted Dec 12, 2006·13 cites·7 claims
- 2567US8927361B2High threshold voltage NMOS transistors for low power IC technologyIBM·Filed 2013·Granted Jan 6, 2015·2 cites·9 claims
- 2666US8148221B2Double anneal with improved reliability for dual contact etch stop liner schemeLIM KHEE YONG·Filed 2009·Granted Apr 3, 2012·3 cites·34 claims
- 2766US8097516B2Dual trench isolation for CMOS with hybrid orientationsCHAN VICTOR·Filed 2008·Granted Jan 17, 2012·2 cites·6 claims
- 2864US8012821B2Semiconductor embedded resistor generationSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Sep 6, 2011·3 cites·21 claims
- 2961US11309221B2Single metallization scheme for gate, source, and drain contact integrationIBM·Filed 2019·Granted Apr 19, 2022·0 cites·20 claims
- 3061US7615433B2Double anneal with improved reliability for dual contact etch stop liner schemeCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 10, 2009·1 cites·25 claims
- 3161US7396724B2Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicalsIBM·Filed 2005·Granted Jul 8, 2008·2 cites·18 claims
- 3261US7314790B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2006·Granted Jan 1, 2008·1 cites·15 claims
- 3359US11257716B2Self-aligned gate cap including an etch-stop layerIBM·Filed 2019·Granted Feb 22, 2022·0 cites·9 claims
- 3458US10229984B2Gap fill of metal stack in replacement gate processIBM·Filed 2017·Granted Mar 12, 2019·0 cites·20 claims
- 3558US7436169B2Mechanical stress characterization in semiconductor deviceIBM·Filed 2005·Granted Oct 14, 2008·1 cites·2 claims
- 3657US10985076B2Single metallization scheme for gate, source, and drain contact integrationIBM·Filed 2018·Granted Apr 20, 2021·0 cites·13 claims
- 3755US9935174B2Gap fill of metal stack in replacement gate processIBM·Filed 2016·Granted Apr 3, 2018·0 cites·20 claims
- 3854US7943486B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2008·Granted May 17, 2011·0 cites·11 claims
- 3954US2004260620A1Storepath for sharing commerce assetsIBM·Filed 2003·Application pending·0 cites
- 4053US7462525B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2007·Granted Dec 9, 2008·0 cites·10 claims
- 4153US2008036028A1Dual trench isolation for cmos with hybrid orientationsIBM·Filed 2007·Application pending·0 cites
- 4249US7161169B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2004·Granted Jan 9, 2007·2 cites·7 claims
- 4349US2007040235A1Dual trench isolation for CMOS with hybrid orientationsIBM·Filed 2005·Application pending·0 cites
- 4447US2006040497A1Material for contact etch layer to enhance device performanceCHAKRAVARTI ASHIMA B·Filed 2005·Application pending·0 cites
- 4544US2005067620A1Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafersIBM·Filed 2004·Application pending·0 cites
- 4643US2006293967A1Gift registry management through business contexts in a service oriented architectureIBM·Filed 2005·Application pending·0 cites
- 4742US2006247936A1Business Activity Creation Using Business Context Services for Adaptable Service Oriented Architecture ComponentsIBM·Filed 2005·Application pending·0 cites
- 4840US2008026523A1Structure and method to implement dual stressor layers with improved silicide controlCHARTERED SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 4940US2006224424A1Business context services for adaptable service oriented architecture componentsIBM·Filed 2005·Application pending·0 cites
- 5035US8969969B2High threshold voltage NMOS transistors for low power IC technologyCHAN VICTOR W C·Filed 2010·Granted Mar 3, 2015·0 cites·10 claims
Showing the top 50 of 51 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →