Inventor · disambiguated record
Vijai Kumar Chhagan
Also filed as: CHHAGAN VIJAI KUMAR · CHHAGAN VIJAI KUMAR N
7 granted patents·1 pending application·237 citations·filing 1998–2003
88Inventor score
Files withCHARTERED SEMICONDUCTOR MFG8
Top patents by PatentIndex Score
8 records- 0192US6337262B1Self aligned T-top gate process integrationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jan 8, 2002·90 cites·5 claims
- 0286US6391732B1Method to form self-aligned, L-shaped sidewall spacersCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted May 21, 2002·45 cites·16 claims
- 0381US6228770B1Method to form self-sealing air gaps between metal interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted May 8, 2001·35 cites·20 claims
- 0476US6387765B2Method for forming an extended metal gate using a damascene processCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 14, 2002·19 cites·11 claims
- 0570US6249035B1LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effectCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 19, 2001·17 cites·3 claims
- 0655US6534393B1Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivityCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Mar 18, 2003·19 cites·30 claims
- 0745US6071793ALocos mask for suppression of narrow space field oxide thinning and oxide punch through effectCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Jun 6, 2000·12 cites·14 claims
- 0836US2003143828A1Novel method of fabricating metallic local interconnections that also improves transistor performanceCHARTERED SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →