Inventor · disambiguated record
Viren Khandekar
Also filed as: KHANDEKAR VIREN · KHANDEKAR VIREN V
24 granted patents·3 pending applications·280 citations·filing 2004–2020
96Inventor score
Files withMAXIM INTEGRATED PRODUCTS18INTEL CORP3KELKAR AMIT SUBHASH1KHANDEKAR VIREN1KHANDEKAR VIREN V1
Top patents by PatentIndex Score
27 records- 0195US9324687B1Wafer-level passive device integrationMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Apr 26, 2016·26 cites·20 claims
- 0293US8643150B1Wafer-level package device having solder bump assemblies that include an inner pillar structureXU YONG L·Filed 2012·Granted Feb 4, 2014·27 cites·10 claims
- 0393US8575493B1Integrated circuit device having extended under ball metallizationXU YONG LI·Filed 2011·Granted Nov 5, 2013·41 cites·8 claims
- 0491US9087732B1Wafer-level package device having solder bump assemblies that include an inner pillar structureMAXIM INTEGRATED PRODUCTS·Filed 2014·Granted Jul 21, 2015·11 cites·9 claims
- 0591US7135771B1Self alignment features for an electronic assemblyINTEL CORP·Filed 2005·Granted Nov 14, 2006·20 cites·16 claims
- 0690US8084871B2Redistribution layer enhancement to improve reliability of wafer level packagingRAHIM S KAYSAR·Filed 2009·Granted Dec 27, 2011·44 cites·18 claims
- 0788US9721912B2Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionalityMAXIM INTEGRATED PRODUCTS·Filed 2014·Granted Aug 1, 2017·10 cites·12 claims
- 0886US9190391B2Three-dimensional chip-to-wafer integrationKELKAR AMIT SUBHASH·Filed 2011·Granted Nov 17, 2015·13 cites·8 claims
- 0986US7482199B2Self alignment features for an electronic assemblyINTEL CORP·Filed 2006·Granted Jan 27, 2009·11 cites·20 claims
- 1085US9040408B1Techniques for wafer-level processing of QFN packagesMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted May 26, 2015·12 cites·22 claims
- 1183US7569939B2Self alignment features for an electronic assemblyINTEL CORP·Filed 2006·Granted Aug 4, 2009·9 cites·14 claims
- 1282US10804233B1Wafer-level chip-scale package device having bump assemblies configured to maintain standoff heightKHANDEKAR VIREN·Filed 2011·Granted Oct 13, 2020·10 cites·12 claims
- 1380US9583425B2Solder fatigue arrest for wafer level packageMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Feb 28, 2017·6 cites·8 claims
- 1475US9093333B1Integrated circuit device having extended under ball metallizationMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Jul 28, 2015·3 cites·6 claims
- 1571US7190078B2Interlocking via for package via integrityKHANDEKAR VIREN V·Filed 2004·Granted Mar 13, 2007·33 cites·11 claims
- 1668US8860222B2Techniques for wafer-level processing of QFN packagesMAXIM INTEGRATED PRODUCTS·Filed 2012·Granted Oct 14, 2014·2 cites·11 claims
- 1763US9087779B2Multi-die, high current wafer level packageMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Jul 21, 2015·1 cites·11 claims
- 1860US10304758B1Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active waferMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted May 28, 2019·1 cites·5 claims
- 1954US9472451B2Technique for wafer-level processing of QFN packagesMAXIM INTEGRATED PRODUCTS·Filed 2014·Granted Oct 18, 2016·0 cites·7 claims
- 2047US9230903B2Multi-die, high current wafer level packageMAXIM INTEGRATED PRODUCTS·Filed 2015·Granted Jan 5, 2016·0 cites·4 claims
- 2146US10032749B2Three-dimensional chip-to-wafer integrationMAXIM INTEGRATED PRODUCTS·Filed 2015·Granted Jul 24, 2018·0 cites·11 claims
- 2246US2010072615A1High-Electrical-Current Wafer Level Packaging, High-Electrical-Current WLP Electronic Devices, and Methods of Manufacture ThereofMAXIM INTEGRATED PRODUCTS·Filed 2008·Application pending·0 cites
- 2345US9219043B2Wafer-level package device having high-standoff peripheral solder bumpsMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Dec 22, 2015·0 cites·20 claims
- 2442US9425064B2Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packagesMAXIM INTEGRATED PRODUCTS·Filed 2012·Granted Aug 23, 2016·0 cites·15 claims
- 2542US2014252571A1Wafer-level package mitigated undercutMAXIM INTEGRATED PRODUCTS·Filed 2013·Application pending·0 cites
- 2640US11428735B1System for monitoring and controlling an integrated circuit testing machineMAXIM INTEGRATED PRODUCTS·Filed 2020·Granted Aug 30, 2022·0 cites·17 claims
- 2731US2011233756A1Wafer level packaging with heat dissipationMAXIM INTEGRATED PRODUCTS·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →