Inventor · disambiguated record
Vivek Kozhikkottu
Also filed as: KOZHIKKOTTU VIVEK JOY · Kozhikkottu Vivek
11 granted patents·5 pending applications·10 citations·filing 2016–2021
82Inventor score
Files withINTEL CORP16
Top patents by PatentIndex Score
16 records- 0183US10319461B2Low-overhead mechanism to detect address faults in ECC-protected memoriesINTEL CORP·Filed 2016·Granted Jun 11, 2019·5 cites·19 claims
- 0270US10884853B2Fast search of error correction code (ECC) protected data in a memoryINTEL CORP·Filed 2019·Granted Jan 5, 2021·2 cites·15 claims
- 0369US11144466B2Memory device with local cache arrayINTEL CORP·Filed 2019·Granted Oct 12, 2021·1 cites·20 claims
- 0468US10860419B2Minimal aliasing bit-error correction codeINTEL CORP·Filed 2018·Granted Dec 8, 2020·1 cites·20 claims
- 0567US11281616B2Programmable data bus inversion and configurable implementationINTEL CORP·Filed 2019·Granted Mar 22, 2022·1 cites·20 claims
- 0651US12271305B2Two-level main memory hierarchy managementINTEL CORP·Filed 2021·Granted Apr 8, 2025·0 cites·19 claims
- 0751US10936507B2System, apparatus and method for application specific address mappingINTEL CORP·Filed 2019·Granted Mar 2, 2021·0 cites·20 claims
- 0850US10862622B2Error correction code (ECC) and data bus inversion (DBI) encodingINTEL CORP·Filed 2019·Granted Dec 8, 2020·0 cites·20 claims
- 0949US11216386B2Techniques for setting a 2-level auto-close timer to access a memory deviceINTEL CORP·Filed 2019·Granted Jan 4, 2022·0 cites·21 claims
- 1047US10268585B2Memory controller that forces prefetches in response to a present row address change timing constraintINTEL CORP·Filed 2016·Granted Apr 23, 2019·0 cites·20 claims
- 1144US2023091205A1Memory side prefetch architecture for improved memory bandwidthINTEL CORP·Filed 2021·Application pending·0 cites
- 1237US10853300B2Low latency statistical data bus inversion for energy reductionINTEL CORP·Filed 2017·Granted Dec 1, 2020·0 cites·18 claims
- 1337US2018285252A1Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality dataINTEL CORP·Filed 2017·Application pending·0 cites
- 1437US2019332469A1Address range based in-band memory error-correcting code protection module with syndrome bufferINTEL CORP·Filed 2019·Application pending·0 cites
- 1533US2018188976A1Increasing read pending queue capacity to increase memory bandwidthINTEL CORP·Filed 2016·Application pending·0 cites
- 1630US2017286216A1Energy efficient read/write support for a protected memoryINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →