Inventor · disambiguated record
Victor R. Nastasi
Also filed as: NASTASI VICTOR R · NASTASI VICTOR RAY
10 granted patents·1 pending application·439 citations·filing 1986–2001
91Inventor score
Top patents by PatentIndex Score
11 records- 0195US4666556ATrench sidewall isolation by polysilicon oxidationIBM·Filed 1986·Granted May 19, 1987·236 cites·26 claims
- 0279US5721448AIntegrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst materialIBM·Filed 1996·Granted Feb 24, 1998·45 cites·7 claims
- 0378US5824580AMethod of manufacturing an insulated gate field effect transistorIBM·Filed 1996·Granted Oct 20, 1998·56 cites·9 claims
- 0460US5804490AMethod of filling shallow trenchesIBM·Filed 1997·Granted Sep 8, 1998·27 cites·6 claims
- 0560US5331199ABipolar transistor with reduced topographyIBM·Filed 1993·Granted Jul 19, 1994·28 cites·5 claims
- 0648US6372573B2Self-aligned trench capacitor capping process for high density DRAM cellsTOSHIBA KK·Filed 1999·Granted Apr 16, 2002·10 cites·14 claims
- 0747US6518145B1Methods to control the threshold voltage of a deep trench corner deviceIBM·Filed 1998·Granted Feb 11, 2003·10 cites·10 claims
- 0844US5234846AMethod of making bipolar transistor with reduced topographyIBM·Filed 1992·Granted Aug 10, 1993·15 cites·10 claims
- 0940US5757059AInsulated gate field effect transistorIBM·Filed 1996·Granted May 26, 1998·9 cites·7 claims
- 1035US2002179997A1Self-aligned corner Vt enhancement with isolation channel stop by ion implantationIBM·Filed 2001·Application pending·0 cites
- 1130US5385850AMethod of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layerIBM·Filed 1991·Granted Jan 31, 1995·3 cites·9 claims
Join the waitlist — get patent alerts
Get an alert when Victor R. Nastasi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →