Inventor · disambiguated record
Viresh Paruthi
Also filed as: PARUTHI VIRESH
110 granted patents·12 pending applications·716 citations·filing 2000–2023
99Inventor score
Top patents by PatentIndex Score
122 records- 0194US11150298B1Converting formal verification testbench drivers with nondeterministic inputs to simulation monitorsIBM·Filed 2020·Granted Oct 19, 2021·5 cites·20 claims
- 0293US11663381B2Clock mapping in an integrated circuit designIBM·Filed 2021·Granted May 30, 2023·4 cites·24 claims
- 0392US7299432B2Method for preserving constraints during sequential reparameterizationIBM·Filed 2005·Granted Nov 20, 2007·29 cites·20 claims
- 0490US7882473B2Sequential equivalence checking for asynchronous verificationIBM·Filed 2007·Granted Feb 1, 2011·28 cites·21 claims
- 0590US6473884B1Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysisIBM·Filed 2000·Granted Oct 29, 2002·77 cites·21 claims
- 0689US7260799B2Exploiting suspected redundancy for enhanced design verificationIBM·Filed 2005·Granted Aug 21, 2007·21 cites·20 claims
- 0788US10970444B1Methods and systems to verify correctness of bug fixes in integrated circuitsIBM·Filed 2020·Granted Apr 6, 2021·4 cites·20 claims
- 0888US7437690B2Method for predicate-based compositional minimization in a verification environmentIBM·Filed 2005·Granted Oct 14, 2008·18 cites·5 claims
- 0988US7356792B2Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solverIBM·Filed 2006·Granted Apr 8, 2008·14 cites·5 claims
- 1087US7367002B2Method and system for parametric reduction of sequential designsIBM·Filed 2005·Granted Apr 29, 2008·16 cites·7 claims
- 1185US7448005B2Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solverIBM·Filed 2006·Granted Nov 4, 2008·13 cites·3 claims
- 1285US7315996B2Method and system for performing heuristic constraint simplificationIBM·Filed 2005·Granted Jan 1, 2008·11 cites·7 claims
- 1385US7290229B2Method and system for optimized handling of constraints during symbolic simulationIBM·Filed 2005·Granted Oct 30, 2007·16 cites·20 claims
- 1484US9436582B1Calculating an immediate parent assertion statement for program verificationIBM·Filed 2015·Granted Sep 6, 2016·5 cites·20 claims
- 1584US7421669B2Using constraints in design verificationIBM·Filed 2005·Granted Sep 2, 2008·12 cites·5 claims
- 1684US7380222B2Method and system for performing minimization of input count during structural netlist overapproximationIBM·Filed 2005·Granted May 27, 2008·11 cites·5 claims
- 1784US6698003B2Framework for multiple-engine based verification tools for integrated circuitsIBM·Filed 2001·Granted Feb 24, 2004·38 cites·28 claims
- 1883US9471327B2Verifying forwarding paths in pipelinesIBM·Filed 2013·Granted Oct 18, 2016·7 cites·7 claims
- 1983US7917874B2Reversing the effects of sequential reparameterization on tracesIBM·Filed 2008·Granted Mar 29, 2011·9 cites·6 claims
- 2083US7765514B2Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variablesIBM·Filed 2007·Granted Jul 27, 2010·9 cites·5 claims
- 2183US7370298B2Method for heuristic preservation of critical inputs during sequential reparameterizationIBM·Filed 2005·Granted May 6, 2008·11 cites·7 claims
- 2283US7203915B2Method for retiming in the presence of verification constraintsIBM·Filed 2005·Granted Apr 10, 2007·13 cites·20 claims
- 2382US8042078B2Enhancing formal design verification by reusing previous resultsIBM·Filed 2009·Granted Oct 18, 2011·13 cites·18 claims
- 2482US7350166B2Method and system for reversing the effects of sequential reparameterization on tracesIBM·Filed 2005·Granted Mar 25, 2008·9 cites·7 claims
- 2582US7350179B2Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variablesIBM·Filed 2005·Granted Mar 25, 2008·9 cites·6 claims
- 2682US7340694B2Method and system for reduction of XOR/XNOR subexpressions in structural design representationsIBM·Filed 2005·Granted Mar 4, 2008·9 cites·7 claims
- 2781US9459878B2Verifying forwarding paths in pipelinesIBM·Filed 2014·Granted Oct 4, 2016·6 cites·4 claims
- 2881US7752593B2Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variablesIBM·Filed 2007·Granted Jul 6, 2010·8 cites·6 claims
- 2981US7360185B2Design verification using sequential and combinational transformationsIBM·Filed 2005·Granted Apr 15, 2008·11 cites·5 claims
- 3081US7350169B2Method and system for enhanced verification through structural target decompositionIBM·Filed 2005·Granted Mar 25, 2008·8 cites·7 claims
- 3180US7266795B2System and method for engine-controlled case splitting within multiple-engine based verification frameworkIBM·Filed 2005·Granted Sep 4, 2007·10 cites·19 claims
- 3279US7779378B2Computer program product for extending incremental verification of circuit design to encompass verification restraintsIBM·Filed 2008·Granted Aug 17, 2010·8 cites·4 claims
- 3379US7689943B2Parametric reduction of sequential designIBM·Filed 2008·Granted Mar 30, 2010·8 cites·13 claims
- 3479US7475370B2System for verification using reachability overapproximationIBM·Filed 2007·Granted Jan 6, 2009·7 cites·7 claims
- 3579US7302656B2Method and system for performing functional verification of logic circuitsIBM·Filed 2006·Granted Nov 27, 2007·13 cites·12 claims
- 3678US7934180B2Incremental speculative mergingIBM·Filed 2008·Granted Apr 26, 2011·8 cites·19 claims
- 3778US7793242B2Method and system for performing heuristic constraint simplificationIBM·Filed 2007·Granted Sep 7, 2010·6 cites·7 claims
- 3878US7788616B2Method and system for performing heuristic constraint simplificationIBM·Filed 2007·Granted Aug 31, 2010·6 cites·6 claims
- 3977US8640065B2Circuit verification using computational algebraic geometryJANSSEN GRADUS GEERT·Filed 2012·Granted Jan 28, 2014·7 cites·22 claims
- 4077US7509605B2Extending incremental verification of circuit design to encompass verification restraintsIBM·Filed 2005·Granted Mar 24, 2009·7 cites·4 claims
- 4176US7856609B2Using constraints in design verificationIBM·Filed 2008·Granted Dec 21, 2010·6 cites·8 claims
- 4275US7913205B2Method and system for reversing the effects of sequential reparameterization on tracesIBM·Filed 2008·Granted Mar 22, 2011·5 cites·7 claims
- 4375US7322017B2Method for verification using reachability overapproximationIBM·Filed 2004·Granted Jan 22, 2008·16 cites·7 claims
- 4474US7882470B2Method for heuristic preservation of critical inputs during sequential reparameterizationIBM·Filed 2008·Granted Feb 1, 2011·5 cites·13 claims
- 4574US7849428B2Formally deriving a minimal clock-gating schemeIBM·Filed 2008·Granted Dec 7, 2010·7 cites·20 claims
- 4674US7343573B2Method and system for enhanced verification through binary decision diagram-based target decompositionIBM·Filed 2005·Granted Mar 11, 2008·5 cites·6 claims
- 4772US9280496B2Formal verification of arbitersIBM·Filed 2012·Granted Mar 8, 2016·3 cites·18 claims
- 4872US7996800B2Computer program product for design verification using sequential and combinational transformationsIBM·Filed 2008·Granted Aug 9, 2011·5 cites·5 claims
- 4972US7788615B2Computer program product for verification using reachability overapproximationIBM·Filed 2007·Granted Aug 31, 2010·4 cites·6 claims
- 5071US11675009B2Converting formal verification testbench drivers with nondeterministic inputs to simulation monitorsIBM·Filed 2021·Granted Jun 13, 2023·0 cites·20 claims
Showing the top 50 of 122 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →