Inventor · disambiguated record
Vijayalakshmi Srinivasan
Also filed as: SRINIVASAN VIJAYALAKSHMI
85 granted patents·20 pending applications·774 citations·filing 1999–2024
99Inventor score
Top patents by PatentIndex Score
105 records- 0198US9418721B2Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)IBM·Filed 2014·Granted Aug 16, 2016·52 cites·11 claims
- 0297US11138010B1Loop management in multi-processor dataflow architectureIBM·Filed 2020·Granted Oct 5, 2021·7 cites·20 claims
- 0397US9431084B2Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)IBM·Filed 2014·Granted Aug 30, 2016·34 cites·15 claims
- 0497US9351899B2Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)IBM·Filed 2014·Granted May 31, 2016·27 cites·17 claims
- 0596US8004884B2Iterative write pausing techniques to improve read latency of memory systemsIBM·Filed 2009·Granted Aug 23, 2011·59 cites·25 claims
- 0693US9430240B1Pre-computation slice merging for prefetching in a computer processorIBM·Filed 2015·Granted Aug 30, 2016·12 cites·20 claims
- 0793US7366875B2Method and apparatus for an efficient multi-path trace cache designIBM·Filed 2005·Granted Apr 29, 2008·27 cites·8 claims
- 0893US6560693B1Branch history guided instruction/data prefetchingIBM·Filed 1999·Granted May 6, 2003·221 cites·34 claims
- 0992US9411730B1Private memory table for reduced memory coherence trafficIBM·Filed 2015·Granted Aug 9, 2016·7 cites·13 claims
- 1091US11669489B2Sparse systolic array designIBM·Filed 2021·Granted Jun 6, 2023·2 cites·20 claims
- 1191US7454573B2Cost-conscious pre-emptive cache line displacement and relocation mechanismsIBM·Filed 2005·Granted Nov 18, 2008·25 cites·21 claims
- 1290US10120685B2Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commitsIBM·Filed 2015·Granted Nov 6, 2018·8 cites·20 claims
- 1390US9760490B2Private memory table for reduced memory coherence trafficIBM·Filed 2016·Granted Sep 12, 2017·5 cites·11 claims
- 1490US9298466B2Multi-threaded processor instruction balancing through instruction uncertaintyIBM·Filed 2012·Granted Mar 29, 2016·11 cites·6 claims
- 1589US8417917B2Processor core stacking for efficient collaborationEMMA PHILIP G·Filed 2009·Granted Apr 9, 2013·21 cites·20 claims
- 1688US10936319B2Predicting cache misses using data access behavior and instruction addressIBM·Filed 2018·Granted Mar 2, 2021·4 cites·4 claims
- 1788US7472226B1Methods involving memory cachesIBM·Filed 2008·Granted Dec 30, 2008·18 cites·3 claims
- 1888US7447923B2Systems and methods for mutually exclusive activation of microprocessor resources to control maximum powerIBM·Filed 2005·Granted Nov 4, 2008·18 cites·9 claims
- 1987US7930578B2Method and system of peak power enforcement via autonomous token-based control and managementIBM·Filed 2007·Granted Apr 19, 2011·17 cites·16 claims
- 2086US7493480B2Method and apparatus for prefetching branch history informationIBM·Filed 2002·Granted Feb 17, 2009·45 cites·17 claims
- 2185US7657726B2Context look ahead storage structuresIBM·Filed 2007·Granted Feb 2, 2010·12 cites·20 claims
- 2284US7962695B2Method and system for integrating SRAM and DRAM architecture in set associative cacheIBM·Filed 2007·Granted Jun 14, 2011·14 cites·27 claims
- 2383US10769238B2Matrix multiplication on a systolic arrayIBM·Filed 2019·Granted Sep 8, 2020·2 cites·15 claims
- 2483US10528356B2Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commitsIBM·Filed 2015·Granted Jan 7, 2020·5 cites·16 claims
- 2582US9529723B2Methods of cache preloading on a partition or a context switchIBM·Filed 2015·Granted Dec 27, 2016·2 cites·20 claims
- 2681US9619385B2Single thread cache miss rate estimationIBM·Filed 2015·Granted Apr 11, 2017·3 cites·13 claims
- 2781US7526610B1Sectored cache memoryIBM·Filed 2008·Granted Apr 28, 2009·10 cites·2 claims
- 2880US10241972B2Matrix multiplication on a systolic arrayIBM·Filed 2017·Granted Mar 26, 2019·2 cites·19 claims
- 2979US11620132B2Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instructionIBM·Filed 2019·Granted Apr 4, 2023·2 cites·7 claims
- 3079US11551054B2System-aware selective quantization for performance optimized distributed deep learningIBM·Filed 2019·Granted Jan 10, 2023·3 cites·20 claims
- 3179US9406368B2Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)IBM·Filed 2014·Granted Aug 2, 2016·5 cites·13 claims
- 3277US8285969B2Reducing broadcasts in multiprocessorsKHUBAIB KHUBAIB·Filed 2009·Granted Oct 9, 2012·13 cites·19 claims
- 3377US7134028B2Processor with low overhead predictive supply voltage gating for leakage power reductionIBM·Filed 2003·Granted Nov 7, 2006·28 cites·26 claims
- 3472US8024513B2Method and system for implementing dynamic refresh protocols for DRAM based cacheIBM·Filed 2007·Granted Sep 20, 2011·5 cites·20 claims
- 3571US9766937B2Thread-based cache content saving for task switchingIBM·Filed 2016·Granted Sep 19, 2017·1 cites·14 claims
- 3671US9740496B2Processor with memory-embedded pipeline for table-driven computationIBM·Filed 2013·Granted Aug 22, 2017·2 cites·13 claims
- 3771US9292445B2Non-data inclusive coherent (NIC) directory for cacheIBM·Filed 2014·Granted Mar 22, 2016·2 cites·11 claims
- 3871US7516310B2Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processorIBM·Filed 2006·Granted Apr 7, 2009·5 cites·3 claims
- 3970US10838868B2Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory componentsIBM·Filed 2019·Granted Nov 17, 2020·1 cites·21 claims
- 4070US9323676B2Non-data inclusive coherent (NIC) directory for cacheIBM·Filed 2013·Granted Apr 26, 2016·2 cites·8 claims
- 4170US9182991B2Multi-threaded processor instruction balancing through instruction uncertaintyBUYUKTOSUNOGLU ALPER·Filed 2012·Granted Nov 10, 2015·2 cites·12 claims
- 4268US11263518B2Bi-scaled deep neural networksIBM·Filed 2019·Granted Mar 1, 2022·1 cites·11 claims
- 4367US8521999B2Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken historyEMMA PHILIP G·Filed 2010·Granted Aug 27, 2013·2 cites·24 claims
- 4467US7337271B2Context look ahead storage structuresIBM·Filed 2003·Granted Feb 26, 2008·10 cites·36 claims
- 4566US10963387B2Methods of cache preloading on a partition or a context switchIBM·Filed 2019·Granted Mar 30, 2021·0 cites·20 claims
- 4666US9448835B2Thread-based cache content saving for task switchingIBM·Filed 2014·Granted Sep 20, 2016·1 cites·12 claims
- 4766US9436501B2Thread-based cache content saving for task switchingIBM·Filed 2014·Granted Sep 6, 2016·1 cites·7 claims
- 4865US8108609B2Structure for implementing dynamic refresh protocols for DRAM based cacheBARTH JOHN E·Filed 2008·Granted Jan 31, 2012·5 cites·10 claims
- 4965US7401209B2Limiting entries searched in load reorder queue to between two pointers for match with executing load instructionIBM·Filed 2006·Granted Jul 15, 2008·2 cites·1 claims
- 5064US10007523B2Predicting cache misses using data access behavior and instruction addressSRINIVASAN VIJAYALAKSHMI·Filed 2011·Granted Jun 26, 2018·2 cites·18 claims
Showing the top 50 of 105 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →