Inventor · disambiguated record
Vivek Thirtha
Also filed as: THIRTHA VIVEK
3 granted patents·8 pending applications·0 citations·filing 2019–2024
42Inventor score
Files withINTEL CORP11
Top patents by PatentIndex Score
11 records- 0167US2023163215A1Gate-all-around integrated circuit structures having fin stack isolationINTEL CORP·Filed 2023·Application pending·0 cites
- 0263US11594637B2Gate-all-around integrated circuit structures having fin stack isolationINTEL CORP·Filed 2020·Granted Feb 28, 2023·0 cites·13 claims
- 0355US2022416041A1Nanoribbon subfin isolation by backside silicon substrate removal with epi protectionINTEL CORP·Filed 2021·Application pending·0 cites
- 0455US2025311322A1Within stack nanoribbon thickness tuning for improved gate-all-around transistor performanceINTEL CORP·Filed 2024·Application pending·0 cites
- 0554US2025220944A1Method of controlling metal gate height and selective spacer formationINTEL CORP·Filed 2023·Application pending·0 cites
- 0651US12414327B2Lateral confinement of source drain epitaxial growth in non-planar transistor for cell height scalingINTEL CORP·Filed 2021·Granted Sep 9, 2025·0 cites·19 claims
- 0751US2025220969A1Gate-all-around devices with different gate lengthsINTEL CORP·Filed 2023·Application pending·0 cites
- 0848US11569370B2DEPOP using cyclic selective spacer etchINTEL CORP·Filed 2019·Granted Jan 31, 2023·0 cites·18 claims
- 0948US2023197818A1Formation of cavity spacer and source-drain epitaxial growth for scaling of gate-all-around transistorsINTEL CORP·Filed 2021·Application pending·0 cites
- 1047US2024006512A1In-situ multi-layer dielectric films for application as gate spacer and etch stop layersINTEL CORP·Filed 2022·Application pending·0 cites
- 1146US2024071831A1Source and drain regions for laterally adjacent gate-all-around (gaa) pmos and nmosINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →