Inventor · disambiguated record
Vladimir Pentkovski
Also filed as: HUFF THOMAS R · PENTKOVSKI VLADIMIR · PENTKOVSKI VLADIMIR M
41 granted patents·5 pending applications·2,027 citations·filing 1998–2016
99Inventor score
Top patents by PatentIndex Score
46 records- 0194US5995122AMethod and apparatus for parallel conversion of color values from a single precision floating point format to an integer formatINTEL CORP·Filed 1998·Granted Nov 30, 1999·112 cites·49 claims
- 0293US6502115B2Conversion between packed floating point data and packed 32-bit integer data in different architectural registersINTEL CORP·Filed 2001·Granted Dec 31, 2002·50 cites·55 claims
- 0393US6377970B1Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitryINTEL CORP·Filed 1998·Granted Apr 23, 2002·173 cites·32 claims
- 0492US6801208B2System and method for cache sharingINTEL CORP·Filed 2000·Granted Oct 5, 2004·108 cites·25 claims
- 0590US7216138B2Method and apparatus for floating point operations and format conversion operationsINTEL CORP·Filed 2001·Granted May 8, 2007·40 cites·30 claims
- 0687US6292815B1Data conversion between floating point packed format and integer scalar formatINTEL CORP·Filed 1998·Granted Sep 18, 2001·98 cites·36 claims
- 0786US6976131B2Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor systemINTEL CORP·Filed 2002·Granted Dec 13, 2005·54 cites·25 claims
- 0886US6772241B1Selective interrupt delivery to multiple processors having independent operating systemsINTEL CORP·Filed 2000·Granted Aug 3, 2004·42 cites·4 claims
- 0986US6480868B2Conversion from packed floating point data to packed 8-bit integer data in different architectural registersINTEL CORP·Filed 2001·Granted Nov 12, 2002·37 cites·26 claims
- 1085US6266769B1Conversion between packed floating point data and packed 32-bit integer data in different architectural registersINTEL CORP·Filed 1998·Granted Jul 24, 2001·49 cites·25 claims
- 1184US6173393B1System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed dataINTEL CORP·Filed 1998·Granted Jan 9, 2001·133 cites·22 claims
- 1283US6202129B1Shared cache structure for temporal and non-temporal information using indicative bitsINTEL CORP·Filed 1998·Granted Mar 13, 2001·94 cites·51 claims
- 1381US7512498B2Streaming processing of biological sequence matchingINTEL CORP·Filed 2002·Granted Mar 31, 2009·4 cites·12 claims
- 1480US7467286B2Executing partial-width packed data instructionsINTEL CORP·Filed 2005·Granted Dec 16, 2008·8 cites·29 claims
- 1580US6584547B2Shared cache structure for temporal and non-temporal instructionsINTEL CORP·Filed 2001·Granted Jun 24, 2003·26 cites·15 claims
- 1679US6819321B1Method and apparatus for processing 2D operations in a tiled graphics architectureINTEL CORP·Filed 2000·Granted Nov 16, 2004·26 cites·20 claims
- 1779US6643745B1Method and apparatus for prefetching data into cacheINTEL CORP·Filed 1998·Granted Nov 4, 2003·93 cites·20 claims
- 1879US6122715AMethod and system for optimizing write combining performance in a shared buffer structureINTEL CORP·Filed 1998·Granted Sep 19, 2000·84 cites·22 claims
- 1978US6192467B1Executing partial-width packed data instructionsINTEL CORP·Filed 1998·Granted Feb 20, 2001·82 cites·43 claims
- 2077US8065555B2System and method for error correction in cache unitsMAIYURAN SUBRAMANIAM·Filed 2006·Granted Nov 22, 2011·11 cites·28 claims
- 2177US6073210ASynchronization of weakly ordered write combining operations using a fencing mechanismINTEL CORP·Filed 1998·Granted Jun 6, 2000·76 cites·20 claims
- 2276US6223258B1Method and apparatus for implementing non-temporal loadsINTEL CORP·Filed 1998·Granted Apr 24, 2001·77 cites·18 claims
- 2375US7516307B2Processor for computing a packed sum of absolute differences and packed multiply-addINTEL CORP·Filed 2001·Granted Apr 7, 2009·18 cites·12 claims
- 2475US6976099B2Selective interrupt delivery to multiple processors having independent operating systemsINTEL CORP·Filed 2004·Granted Dec 13, 2005·19 cites·16 claims
- 2575US6247116B1Conversion from packed floating point data to packed 16-bit integer data in different architectural registersINTEL CORP·Filed 1998·Granted Jun 12, 2001·69 cites·41 claims
- 2674US6243803B1Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitryINTEL CORP·Filed 1998·Granted Jun 5, 2001·66 cites·22 claims
- 2773US6263426B1Conversion from packed floating point data to packed 8-bit integer data in different architectural registersINTEL CORP·Filed 1998·Granted Jul 17, 2001·55 cites·19 claims
- 2873US6122725AExecuting partial-width packed data instructionsINTEL CORP·Filed 1998·Granted Sep 19, 2000·65 cites·13 claims
- 2970US6970994B2Executing partial-width packed data instructionsINTEL CORP·Filed 2001·Granted Nov 29, 2005·12 cites·117 claims
- 3068US6085312AMethod and apparatus for handling imprecise exceptionsINTEL CORP·Filed 1998·Granted Jul 4, 2000·50 cites·28 claims
- 3164US7114011B2Multiprocessor-scalable streaming data server arrangementINTEL CORP·Filed 2001·Granted Sep 26, 2006·13 cites·38 claims
- 3264US6748512B2Method and apparatus for mapping address space of integrated programmable devices within host system memoryINTEL CORP·Filed 2000·Granted Jun 8, 2004·10 cites·37 claims
- 3363US6356270B2Efficient utilization of write-combining buffersINTEL CORP·Filed 1998·Granted Mar 12, 2002·40 cites·17 claims
- 3462US9632790B2Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program orderINTEL CORP·Filed 2012·Granted Apr 25, 2017·2 cites·21 claims
- 3561US6205520B1Method and apparatus for implementing non-temporal storesINTEL CORP·Filed 1998·Granted Mar 20, 2001·38 cites·19 claims
- 3657US6978357B1Method and apparatus for performing cache segment flush and cache segment invalidation operationsINTEL CORP·Filed 1998·Granted Dec 20, 2005·32 cites·38 claims
- 3753US9529596B2Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bitsBABAYAN BORIS A·Filed 2011·Granted Dec 27, 2016·1 cites·12 claims
- 3853US6466217B1Method and apparatus for ensuring backward compatibility in a bucket rendering systemINTEL CORP·Filed 1999·Granted Oct 15, 2002·20 cites·26 claims
- 3948US2017235578A1Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order ProcessorINTEL CORP·Filed 2016·Application pending·0 cites
- 4045US2010274972A1Systems, methods, and apparatuses for parallel computingBABAYAN BORIS·Filed 2009·Application pending·0 cites
- 4144US6369813B2Processing polygon meshes using mesh pool windowINTEL CORP·Filed 1998·Granted Apr 9, 2002·13 cites·20 claims
- 4242US6223276B1Pipelined processing of short data streams using data prefetchingINTEL CORP·Filed 1998·Granted Apr 24, 2001·13 cites·24 claims
- 4341US6275904B1Cache pollution avoidance instructionsINTEL CORP·Filed 1998·Granted Aug 14, 2001·14 cites·18 claims
- 4439US2002073264A1Integrated co-processor configured as a PCI deviceFiled 2000·Application pending·0 cites
- 4536US2004003018A1Method and system for efficient handlings of serial and parallel java operationsFiled 2002·Application pending·0 cites
- 4633US2014208074A1Instruction scheduling for a multi-strand out-of-order processorBABAYAN BORIS A·Filed 2012·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Vladimir Pentkovski files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →