Inventor · disambiguated record
Vojislav Vukovic
Also filed as: VUKOVIC VOJISLAV
10 granted patents·2 pending applications·20 citations·filing 2002–2020
83Inventor score
Top patents by PatentIndex Score
12 records- 0160US6665850B1Spanning tree method for K-dimensional spaceLSI LOGIC CORP·Filed 2002·Granted Dec 16, 2003·8 cites·23 claims
- 0257US7493519B2RRAM memory error emulationLSI CORP·Filed 2005·Granted Feb 17, 2009·1 cites·4 claims
- 0357US7028274B1RRAM backend flowLSI LOGIC CORP·Filed 2005·Granted Apr 11, 2006·1 cites·6 claims
- 0455US8035537B2Methods and apparatus for programmable decoding of a plurality of code typesLSI CORP·Filed 2008·Granted Oct 11, 2011·3 cites·18 claims
- 0551US8095845B1System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding unitsANDREEV ALEXANDER E·Filed 2008·Granted Jan 10, 2012·2 cites·10 claims
- 0650US7096413B2Decomposer for parallel turbo decoding, process and integrated circuitLSI LOGIC CORP·Filed 2002·Granted Aug 22, 2006·5 cites·16 claims
- 0750US2020289609A1Peptidomimetic macrocycles and uses thereofAILERON THERAPEUTICS INC·Filed 2020·Application pending·0 cites
- 0841US8769372B2System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding unitsANDREEV ALEXANDER E·Filed 2011·Granted Jul 1, 2014·0 cites·20 claims
- 0939US2006236194A1Decomposer for parallel turbo decoding, process and integrated circuitLSI LOGIC CORP·Filed 2006·Application pending·0 cites
- 1035US7739575B2Pipelined LDPC arithmetic unitLSI CORP·Filed 2007·Granted Jun 15, 2010·0 cites·1 claims
- 1135US7313660B2Data stream frequency reduction and/or phase shiftLSI CORP·Filed 2003·Granted Dec 25, 2007·0 cites·15 claims
- 1231US8438641B2Security protocol processing for anti-replay protectionVUKOVIC VOJISLAV·Filed 2010·Granted May 7, 2013·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →