Inventor · disambiguated record
W. Story Leavesley, Iii
Also filed as: LEAVESLEY III W STORY
10 granted patents·219 citations·filing 2004–2011
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0195US7619442B1Versatile bus interface macro for dynamically reconfigurable designsXILINX INC·Filed 2008·Granted Nov 17, 2009·58 cites·3 claims
- 0295US7478357B1Versatile bus interface macro for dynamically reconfigurable designsXILINX INC·Filed 2006·Granted Jan 13, 2009·65 cites·17 claims
- 0385US7941777B1Generating a module interface for partial reconfiguration design flowsXILINX INC·Filed 2007·Granted May 10, 2011·13 cites·17 claims
- 0482US7392498B1Method and apparatus for implementing a pre-implemented circuit design for a programmable logic deviceXILINX INC·Filed 2004·Granted Jun 24, 2008·41 cites·19 claims
- 0580US8286113B1Verification of logic core implementationBRIDGFORD BRENDAN K·Filed 2011·Granted Oct 9, 2012·8 cites·20 claims
- 0679US7620927B1Method and apparatus for circuit design closure using partitionsXILINX INC·Filed 2006·Granted Nov 17, 2009·11 cites·20 claims
- 0777US7490312B1Partition-based incremental implementation flow for use with a programmable logic deviceXILINX INC·Filed 2006·Granted Feb 10, 2009·9 cites·16 claims
- 0875US7590951B1Plug-in component-based dependency management for partitions within an incremental implementation flowXILINX INC·Filed 2006·Granted Sep 15, 2009·9 cites·20 claims
- 0969US8332788B1Generating a module interface for partial reconfiguration design flowsYOUNG JAY T·Filed 2011·Granted Dec 11, 2012·3 cites·18 claims
- 1059US7810055B1Design independent correlation data storage for use with physical design of programmable logic devicesXILINX INC·Filed 2006·Granted Oct 5, 2010·2 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →