Inventor · disambiguated record
Warren E. Cory
Also filed as: CORY WARREN E
22 granted patents·486 citations·filing 2002–2023
96Inventor score
Top patents by PatentIndex Score
22 records- 0194US10528513B1Circuit for and method of providing a programmable connector of an integrated circuit deviceXILINX INC·Filed 2018·Granted Jan 7, 2020·16 cites·20 claims
- 0293US8245102B1Error checking parity and syndrome of a block of data with relocated parity bitsCORY WARREN E·Filed 2008·Granted Aug 14, 2012·23 cites·18 claims
- 0393US7913104B1Method and apparatus for receive channel data alignment with minimized latency variationXILINX INC·Filed 2007·Granted Mar 22, 2011·36 cites·20 claims
- 0492US10038450B1Circuits for and methods of transmitting data in an integrated circuitXILINX INC·Filed 2015·Granted Jul 31, 2018·12 cites·20 claims
- 0592US6617877B1Variable data width operation in multi-gigabit transceivers on a programmable logic deviceXILINX INC·Filed 2002·Granted Sep 9, 2003·77 cites·33 claims
- 0691US7623660B1Method and system for pipelined decryptionXILINX INC·Filed 2005·Granted Nov 24, 2009·27 cites·76 claims
- 0789US10623174B1Low latency data transfer technique for mesochronous divided clocksXILINX INC·Filed 2018·Granted Apr 14, 2020·9 cites·20 claims
- 0889US8411703B1Method and apparatus for a reduced lane-lane skew, low-latency transmission systemCORY WARREN E·Filed 2009·Granted Apr 2, 2013·23 cites·7 claims
- 0988US7519747B1Variable latency buffer and method of operationXILINX INC·Filed 2003·Granted Apr 14, 2009·57 cites·5 claims
- 1086US10033523B1Circuit for and method of measuring latency in an integrated circuitXILINX INC·Filed 2017·Granted Jul 24, 2018·6 cites·20 claims
- 1186US6970013B1Variable data width converterXILINX INC·Filed 2003·Granted Nov 29, 2005·46 cites·16 claims
- 1283US7426678B1Error checking parity and syndrome of a block of data with relocated parity bitsXILINX INC·Filed 2004·Granted Sep 16, 2008·21 cites·10 claims
- 1382US7295639B1Distributed adaptive channel bonding control for improved tolerance of inter-channel skewXILINX INC·Filed 2003·Granted Nov 13, 2007·33 cites·29 claims
- 1478US7187709B1High speed configurable transceiver architectureXILINX INC·Filed 2002·Granted Mar 6, 2007·27 cites·17 claims
- 1578US7099426B1Flexible channel bonding and clock correction operations on a multi-block data pathXILINX INC·Filed 2002·Granted Aug 29, 2006·27 cites·35 claims
- 1671US7111220B1Network physical layer with embedded multi-standard CRC generatorXILINX INC·Filed 2002·Granted Sep 19, 2006·16 cites·45 claims
- 1768US7895509B1Error checking parity and syndrome of a block of data with relocated parity bitsXILINX INC·Filed 2008·Granted Feb 22, 2011·4 cites·12 claims
- 1864US7382823B1Channel bonding control logic architectureXILINX INC·Filed 2002·Granted Jun 3, 2008·9 cites·18 claims
- 1964US7088767B1Method and apparatus for operating a transceiver in different data ratesXILINX INC·Filed 2002·Granted Aug 8, 2006·10 cites·11 claims
- 2063US12248761B2Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable latencyXILINX INC·Filed 2023·Granted Mar 11, 2025·0 cites·18 claims
- 2162US6960933B1Variable data width operation in multi-gigabit transceivers on a programmable logic deviceXILINX INC·Filed 2003·Granted Nov 1, 2005·6 cites·18 claims
- 2258US8301988B1Error checking parity and syndrome of a block of data with relocated parity bitsCORY WARREN E·Filed 2011·Granted Oct 30, 2012·1 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →